Deriving Boundary Scan Diagnostic Coverage for High Density ASIC Arrays
Deriving boundary scan coverage for high-density ASIC arrays requires precise accounting of scannable versus un-scannable nets to prevent costly field escapes.
Boundary Register Shift Path
Serial Route
Internal chain linkages within a boundary scan architecture connect the input and output cells of integrated circuits to form a continuous pathway for test data. The boundary register shift path enables the serial transport of stimulus and response bits through the device during board level testing.
Scan Sequence
Operating under the control of the test access port state machine allows the test vector to move through the register on the rising edge of the test clock. The controller drives the test mode select line to shift patterns through the chip boundary cells. Each bit progresses to the next register stage until the complete test frame is loaded.
Once the data rests in the register pins the diagnostic software executes the test vectors.
Hardware Diagnostic
Defects like open solder joints or shorted traces alter the pattern received at the destination register stage. Software analysis maps these discrepancies to locate the exact nets suffering from bridging or open circuit faults. Test systems rely on the integrity of this shift path to isolate faults on high density assemblies where physical probe access is impossible.
Any disruption within the boundary register shift path disables the boundary scan capability of the entire board.