Deriving Boundary Scan Diagnostic Coverage for High Density ASIC Arrays
Deriving boundary scan coverage for high-density ASIC arrays requires precise accounting of scannable versus un-scannable nets to prevent costly field escapes.
Bridging Fault Model
Short Circuitry
Structural fault representations in digital circuit testing assume an unintended conductive pathway connects two distinct signal nets within a fabricated circuit layout. The bridging fault model models physical solder bridges or copper whiskers that force two separate circuit nodes to share a single logic state. Test pattern generation algorithms compute vector sets based on this model to drive one net to a high logic level while observing whether the adjacent net pulls it low.
This analytical model fails to predict circuit behavior when the bridge resistance falls into an intermediate analog regime between a zero-ohm short and an open circuit.
Logic Dominance
Signal contention between driving gates determines the resulting voltage level on bridged conductor lines. Dominant logic models force the combined net state to a logical zero or logical one depending on transistor sizing.
Fault Coverage
Automatic test pattern generation tools calculate the percentage of potential physical short circuits detected by a given digital vector set. Physical layout topology data guides the extraction of adjacent copper trace pairs to restrict fault candidate lists to realistic failure sites. Flying probe testers and automated bed-of-nails fixtures apply these vector sets during post-assembly board screening.
Uncovered bridge locations allow latent manufacturing defects to escape into final product packaging.