Signal Verification
Capacitive Open Detection identifies unbonded component leads during printed circuit board assembly by measuring localized electrostatic field shifts between an overhead probe and the metal pin. Electrical testing equipment applies an alternating current voltage to the integrated circuit package while the sensor scans above the component lands to register parasitic capacitance values against a pre-calibrated baseline. When a pin floats above the solder pad due to coplanarity defects or insufficient paste deposition, the measured coupling capacitance drops significantly below the threshold required for a complete circuit.
This non-contact inspection method operates during the in-circuit test phase following reflow soldering to catch lifted leads before functional verification begins.
Boundary Condition
Substrate thickness variations and adjacent ground planes distort the electrostatic field and introduce false readings unless the fixture software applies dynamic normalization algorithms to compensate for local board geometry. Component packaging materials also restrict measurement accuracy because thick plastic encapsulation or embedded metal heat sinks shield the internal lead frame from the external probe field. Production lines processing double-sided assemblies face high capacitive interference from bottom-side components located directly beneath the test node, which forces engineers to program wider guard bands or switch to alternative boundary scan checks.
Process Integration
Placement machines drop components onto wet solder paste and reflow ovens melt the alloy to form mechanical joints, while subsequent testing steps isolate assembly faults by running automated test scripts through bed-of-nails fixtures and overhead sensors. Manufacturing facilities mount the capacitive probe directly onto the standard fixture deck to execute lead verification during the same handling motion that measures resistance and diode junctions, thus avoiding extra cycle time penalties. Plant operators review failure logs from the open detection cycle to identify upstream stencil printing errors or worn placement nozzles before board defects multiply across the production batch.