Determining Microvia Interface Mechanics under Accelerated Thermal Stress Testing
Microvia interface mechanics dictate that thermal cycling drives out-of-plane dielectric expansion, inducing shear failure at contaminated target pad boundaries.
HDI Fabrication Yield
Process Capability
Production output metrics track the ratio of functional high density interconnect boards to the total number of units started. Achieving a high hdi fabrication yield requires precise control over sequential lamination and laser drilling processes. Complex stackups with multiple microvia layers increase the risk of failure at each stage of the build.
The final number indicates the effectiveness of the registration systems and the chemical plating baths.
Feature Density
Fine lines and tight spaces create more opportunities for shorts or opens during the imaging and etching steps. A lower hdi fabrication yield often stems from the difficulty of cleaning small via holes before copper plating. If the developer cannot reach the bottom of a blind via, the connection fails to form.
Narrow traces are more susceptible to over etching which destroys the circuit path. Precise imaging is required to maintain trace width across the entire panel.
Economic Impact
Profitability of a production run depends on keeping scrap rates low while meeting high technology specifications. A drop in hdi fabrication yield increases the unit cost because the materials and labor of the failed boards are lost. Frequent inspection at intermediate steps helps to identify process drift before large batches are ruined.