Stacked Standard
Industry protocols define a standardized infrastructure for testing three-dimensional integrated circuits through every layer of a die stack. The ieee 1838 test access framework provides a scalable method for reaching deeply embedded components in multi-level semiconductor packages. It establishes a primary port for external communication and a flexible wrapper for individual dies.
This architecture enables vertical data transport between levels.
Layer Connectivity
Each die in the stack incorporates a die wrapper that interfaces with the global test bus. Implementing ieee 1838 test access allows a single entry point on the package base to control and observe logic at the top of the stack. Designers use through-silicon vias to carry the signals through the intermediate silicon layers.
The protocol supports both scan-based testing and built-in self-test routines. Sequential access to different dies prevents excessive power consumption during the test cycle. Logic isolation ensures that a faulty die does not interfere with the evaluation of its neighbors.
Diagnostic Depth
Fault localization becomes possible even after the package is fully assembled. By utilizing ieee 1838 test access, engineers can identify specific die-to-die interconnect failures. Automated test equipment leverages the standard to reduce programming complexity.
Complex 3D assemblies require this level of visibility.
