Sequential Lamination Registration Budgets across High Density Interconnect Stackups
Sequential lamination registration budgets require root-sum-square alignment modeling of sub-core thermal shrinkage and drill offsets to size microvia lands.
Inner Layer Offset
Registration Deviation
The misalignment between different conductive layers in a multilayer circuit board identifies a failure in the lamination or imaging setup. Inner layer offset occurs when the copper patterns on one layer do not line up perfectly with the patterns on the layers above or below it. This displacement can lead to shorts between vias and traces or the loss of annular ring integrity.
Error Source
Material shrinkage during the heating and cooling of the press cycle causes the panels to change size unpredictably. To minimize inner layer offset, fabricators use pinning systems or optical registration cameras to lock the layers in place before lamination. Modern lamination presses include compensation factors that scale the artwork to account for the expected material movement.
Radiographic inspection allows quality control teams to see the alignment of internal pads without destroying the board. If the displacement is too great, the drill bit will miss the center of the target pads and potentially cause an open circuit. Establishing tight tolerances for this parameter is necessary for the production of high-density designs.
Inspection Technique
Optical measurements provide the data needed to adjust the lamination parameters for future batches. When inner layer offset is kept within the design limits, the reliability of the via connections is maintained. This parameter is a key metric for evaluating the capability of a PCB fabricator.