Sequential Lamination Registration Budgets across High Density Interconnect Stackups

Error

Vector Stacking in Sequential Sub-Core Alignment

Layer-to-layer registration is often treated as a simple spatial tolerance, but in multi-stage High Density Interconnect (HDI) builds, it acts as a dynamic vector sum. Every step in a sequential lamination sequence introduces its own directional shifts, rotational skew, and scaling errors. In a standard 1+N+1 stackup, the shop laminates a central sub-core, drills and plates through-holes, etches copper patterns, and applies one dielectric layer to each side before the final press pass.

Advanced 3+N+3 or Every Layer Interconnect (ELIC) designs require three or four separate lamination cycles under high temperature and hydraulic pressure. Each press pass reheats cured dielectric material to 180 to 220 degrees Celsius, triggering secondary cross-linking, resin stress relaxation, and erratic movement across the panel surface.

The overall registration error budget at any given microvia landing layer comes down to four physical factors: substrate material movement, optical tooling uncertainty, mechanical drill axis drift, and photo-imaging distortion. When carbon dioxide or ultraviolet laser ablation drills a microvia on layer 1 to strike a target pad on layer 2, laser steering optics align to outer-layer fiducials. These fiducials trace back to targets etched onto the sub-core during an earlier production stage.

If that sub-core contracts non-linearly during secondary lamination, the actual position of the layer 2 target pad drifts away from the coordinates registered by the laser drill’s vision system.

Understanding this vector sum requires tracking how sub-cores shift relative to the panel center point. Sub-core laminates do not contract uniformly. Their dimensional movement combines a linear scaling factor, expressed in parts per million (PPM), with an uncompensated residual distortion field.

Shops compensate for linear scaling by adjusting photo-mask artwork dimensions during laser direct imaging (LDI) or photolithography. Residual distortion ~ local stretching, bowing, and trapezoidal warping ~ cannot be offset by global scaling factors. This uncompensated residual error sets the minimum physical width of the microvia target pad.

Thermal excursions during secondary lamination convert linear sub-core scaling errors into non-linear spatial distortions across outer panel quadrants.

True Position Deviations across Multiple Lamination Steps

Tracking registration tolerance across N sequential lamination passes shows how rapidly spatial errors accumulate. In a build with multiple sub-cores, like a 2+2+N+2+2 structure, inner sub-cores undergo repeated thermal cycles while outer layers see fewer heat excursions. Layer pairs near the center of the stackup suffer the highest cumulative resin shrinkage and glass fiber distortion.

As lamination cycles add up, the true position deviation of a feature on layer N relative to layer N+1 grows, squeezing the process window for microvia alignment.

Specifying an inner-layer land diameter of 250 micrometers with a 100-micrometer laser-drilled microvia leaves a theoretical overlay clearance of 75 micrometers around the hole circumference. In practice, initial sub-core image placement contributes 12 to 15 micrometers of baseline error. Primary lamination shrinkage adds 15 to 25 micrometers of uncontrolled movement across an 18-by-24-inch production panel.

Secondary lamination of outer layers introduces another 18 to 30 micrometers of non-linear skew. Finally, laser beam positioning error adds 10 to 12 micrometers of random deviation. Adding these tolerances arithmetically gives a worst-case error of 82 micrometers ~ exceeding the 75-micrometer clearance and causing microvia breakout.

Breakout occurs when the laser-drilled hole intersects the outer edge of the target land, exposing the surrounding dielectric interface. Subsequent electroless copper deposition and galvanic plating fill this breakout zone, creating a structural stress concentrator. Under thermal shock testing ~ such as IPC-TM-650 Method 2.6.7.2 fluid immersion or repeated solder reflow passes ~ these asymmetric copper joints generate severe z-axis shear stress, eventually leading to target pad lifting, resin crazing, or open circuits across the layer interface.

Mechanical Pinning Systems versus Optical Alignment Targets

Historically, bare-board fabrication relied on mechanical pin registration systems, such as four-slot post-etch punches, to align inner layers before lamination. Steel pins locked the positions of sub-cores inside press tool plates. While this worked for standard multi-layer rigid boards up to 16 layers, mechanical pinning cannot hit the tight spatial tolerances required for HDI stackups below 50-micrometer trace and space geometry.

Pinned edges remain fixed during heat-up cycles while resin melts and glass fibers expand, forcing the substrate to buckle, bow, or store internal stresses that release unpredictably after cooling and pin removal.

Modern high-density facilities use pinless optical alignment systems for sequential lamination builds. Outer sub-core layers carry vision targets etched into their perimeter margins. High-resolution charge-coupled device (CCD) cameras scan these targets through transparent film or prepreg windows before the sub-stacks are clamped.

Induction spot-welding or high-intensity ultraviolet adhesives lock sub-core layers in place before they enter the hydraulic hot press. Aligning to optical targets decouples panel placement from mechanical plate tolerances, eliminating edge-pin stress concentrations and cutting panel-wide rotational skew by up to 40 percent compared to pin tooling.

Registration tooling choices define a board plant’s baseline capability. A shop using standard post-etch mechanical punch systems holds layer-to-layer registration tolerances of +/- 35 to +/- 50 micrometers. A plant equipped with four-camera optical alignment, LDI vision tracking, and real-time X-ray drill optimization holds +/- 15 to +/- 22 micrometers over the same panel size.

Designing tight microvia target lands for a mechanically aligned shop leads to heavy yield loss and engineering holds asking for pad expansions that ruin routing density.

Choosing between staggered and stacked microvias directly affects the error budget. Staggered microvias spread registration tolerances across separate dielectric interfaces, so each via lands on its own target pad with an isolated tolerance budget. Stacked microvias demand precise vertical alignment across multiple lamination passes.

A microvia on layer 1 landing directly on a filled microvia on layer 2 ~ which in turn sits on layer 3 ~ creates a compound tolerance stack. Spatial errors on layer 2 carry directly into layer 1, doubling the risk of land breakout at the top interface.

A persistent question in shop-floor metrology is whether optical alignment targets placed solely on outer panel margins accurately reflect local material distortion within central active board areas on 24-by-30-inch extra-large panel formats.

Shrink

Dimensional Instability in Reinforced and Unreinforced Dielectrics

Laminate shrinkage during sequential pressing comes down to polymer physics, resin cure state, and glass fabric reinforcement geometry. Standard FR-4 laminates consist of woven E-glass cloth impregnated with epoxy resin. Under heat and pressure, the epoxy passes through its glass transition temperature (Tg), liquefies, fills copper clearances, and cross-links into a solid structural matrix.

During this thermal cycle, chemical bond formation causes volumetric shrinkage. Cross-linking contracts the molecular network, pulling adjacent glass fibers closer together and inducing dimensional strain across the sub-core.

Unreinforced dielectrics ~ such as non-woven resin-coated copper (RCC) foils or pure polyimide and liquid crystal polymer (LCP) films used in ultra-high-density designs ~ behave quite differently from glass-reinforced cores. Reinforced laminates are constrained by woven glass cloth, whose low coefficient of thermal expansion (CTE) of roughly 5 to 6 PPM per degree Celsius suppresses resin expansion along the x and y axes. Unreinforced substrates lack this internal skeleton.

When an RCC film is laminated, its x-y movement is driven entirely by the resin’s high CTE ~ often exceeding 50 to 80 PPM per degree Celsius below Tg ~ resulting in shrinkage three to five times greater than in woven glass sub-cores.

Resin content directly governs sub-core dimensional stability. A high-resin core, like a 1080 glass weave at 68 percent resin content, contracts more during lamination than a low-resin core using a 7628 weave at 43 percent resin content, simply because more polymer volume yields greater cross-linking shrinkage per unit area. Stackups often mix glass styles to meet controlled impedance targets on signal layers while relying on lower-resin structural sub-cores to minimize cumulative registration drift.

However, this structural asymmetry creates differential shrinkage forces across adjacent layers, leading to panel bowing and twisting.

Resin Recure Kinetics and Sub-Core Thermal Hysteresis

When a fully cured sub-core panel undergoes secondary lamination to receive outer prepreg and copper layers, it reheats to or beyond its initial curing threshold. A substrate built with a 170 degree Celsius Tg epoxy exposed to a 190 degree Celsius press profile experiences secondary cure kinetics. Unreacted functional groups in the cross-linked matrix react further, causing minor post-cure volumetric contraction.

At the same time, residual stresses locked into the core during initial manufacture relax under high heat, shifting sub-core dimensions.

Thermal hysteresis is the permanent dimensional offset left in a laminate after it is heated to lamination temperatures and cooled back to ambient conditions. Laminates rarely return to their exact starting coordinates after a thermal cycle. The magnitude of this shift depends on peak temperature, dwell time, cooling rate, and pre-press moisture absorption.

Sub-cores stored in unconditioned room air absorb ambient moisture. When placed into a hot press, that entrapped water turns to steam within resin micropores, accelerating stress relaxation and driving uneven spatial expansion before the matrix consolidates.

To minimize hysteresis errors, high-reliability shops enforce strict baking protocols between processing steps. Subjecting inner-layer cores to a controlled bake before pattern imaging relaxes the polymer network and relieves manufacturing stress prior to photoresist application. This ensures post-etch dimensions reflect the substrate’s equilibrium state.

Skipping this step allows cores to relax after inner-layer features are defined, throwing off artwork scaling factors during final sequential pressing.

Glass Fabric Style Influence on Directional Anisotropy

Woven glass reinforcement introduces directional anisotropy into laminate material movement. Circuit board laminates have two distinct axes: warp, running parallel to the roll length of the glass cloth, and fill (or weft), running perpendicular across its width. Warp threads are pulled under high mechanical tension during weaving and resin impregnation, while fill threads are woven under lower tension.

As a result, glass fabric expands and contracts asymmetrically during lamination thermal cycles.

The warp axis of a laminate core provides greater dimensional stability and lower shrinkage than the fill axis. For a high-performance FR-4 laminate (IPC-4101/126 grade), warp-axis shrinkage typically runs between -150 and -250 PPM, whereas fill-axis shrinkage reaches -350 to -500 PPM under identical press conditions. If sub-core panel blanks are accidentally rotated 90 degrees during preparation, warp and fill axes misalign between adjacent layers.

This cross-axis conflict generates severe internal shear forces during cooling, causing large layer-to-layer registration offsets and warping rectangular panels into rhomboids.

• Woven Glass Fabric 106 carries low glass weight and high resin content, leading to large dimensional movement up to 600 PPM along the fill axis.
• Woven Glass Fabric 1080 offers balanced thread counts per inch, holding warp and fill shrinkage within a tighter 200 to 350 PPM variance band.
• Woven Glass Fabric 2116 uses heavier yarn diameters to provide structural rigidity, keeping fill-direction material movement below 180 PPM.
• Flat Glass Weave 1078 employs spread glass filaments to eliminate weave gaps, providing uniform dielectric constant performance while reducing directional strain anisotropy between axes.

Material selection directly determines the process capability index (Cpk) achieved during sequential lamination. Lower-cost FR-4 laminates (IPC-4101/21) show wider lot-to-lot dimensional variation, forcing fabricators to enlarge microvia target lands to protect yield. Premium high-speed, low-loss substrates (IPC-4101/102, /126, or /131) use tight-tolerance yarn treatments and refined resin systems that yield predictable, repeatable shrinkage.

Designing HDI stackups around high-performance slash-sheet materials allows smaller target lands without raising microvia breakout risks.

Sub-core laminates containing glass weaves with high warp-to-fill anisotropy ratios require separate x-axis and y-axis artwork compensation factors during inner-layer photo-imaging.

Budget

Mathematical Formulation of Registration Tolerances

Designing a reliable sequential HDI stackup requires converting physical manufacturing variations into a statistical spatial budget. Board manufacturing tolerances do not sum linearly; assuming worst-case alignment stackups across eight or ten layers demands impractically large target lands that block dense BGA escape routing. Instead, fabricators rely on Root Sum Square (RSS) statistical modeling, scaled by a process capability coverage factor, to establish realistic registration budgets for sequential builds.

The total registration error radius Rtotal at a given microvia interface is calculated using the vector RSS equation:

Rtotal = k · sqrtσmaterial2 + σartwork2 + σimaging2 + σtooling2 + σdrill2

Where σmaterial represents the standard deviation of sub-core residual movement after linear scaling compensation, σartwork accounts for photolithography film or LDI raster distortion, σimaging captures photoresist edge definition variance, σtooling represents pinless optical positioning accuracy, and σdrill defines laser beam positional offset. The coverage factor k sets the statistical yield target: k = 3 corresponds to 3-sigma limits (99.73 percent yield), while k = 4 covers 4-sigma limits (99.99 percent yield).

In a sequential lamination sequence, each secondary lamination pass introduces another iteration of sub-core material movement and optical alignment variance. For an N-stage sequential build, the material movement variance expands according to the number of heat excursions:

σmaterialtotal2 = sumi=1N σmaterial, i2 · (1 + αrecure, i)

Where αrecure, i is the resin recure instability factor for pass i. This multiplicative relationship explains why adding a third or fourth lamination pass causes non-linear growth in required microvia land diameters.

Root Sum Square Model against Worst-Case Vector Stacks

Evaluating a 3+N+3 sequential lamination stackup on an 18-by-24-inch panel illustrates the practical difference between RSS modeling and worst-case vector summation. The benchmark case traces the alignment of a layer 1 to layer 2 laser-drilled microvia landing on an inner-layer target pad defined on sub-core sub-assembly 2.

The individual process standard deviations (1-sigma tolerances) measured on the shop floor under standard operating conditions are established as follows:

1. Primary sub-core etching image placement holds a standard deviation of 4.2 micrometers.
2. Sub-core 1 thermal lamination residual non-linear movement holds a standard deviation of 8.5 micrometers.
3. Secondary lamination press cycle heat hysteresis holds a standard deviation of 9.1 micrometers.
4. Tertiary lamination press cycle heat hysteresis holds a standard deviation of 11.3 micrometers.
5. LDI optical vision registration targeting accuracy holds a standard deviation of 3.5 micrometers.
6. UV laser drill galvanometric mirror positioning holds a standard deviation of 3.8 micrometers.

Adding these variance components arithmetically to calculate a absolute worst-case error boundary gives:

Rworstcase = 4.2 + 8.5 + 9.1 + 11.3 + 3.5 + 3.8 = 40.4 μm

This worst-case radial error of 40.4 micrometers implies a positional tolerance diameter of 80.8 micrometers. Adding this tolerance to a 100-micrometer laser microvia requires a minimum target land diameter of 180.8 micrometers to prevent breakout under worst-case conditions. Calculating the statistical RSS registration boundary for a 3-sigma (99.73 percent) confidence interval gives:

RRSS = 3 · sqrt4.22 + 8.52 + 9.12 + 11.32 + 3.52 + 3.82 = 3 · sqrt17.64 + 72.25 + 82.81 + 127.69 + 12.25 + 14.44

RRSS = 3 · sqrt327.08 = 3 · 18.08 = 54.26 μm

The statistical 3-sigma radial error equals 54.26 micrometers, translating to a positional tolerance diameter of 108.5 micrometers. Under RSS modeling, a 100-micrometer microvia needs a 208.5-micrometer target land diameter to ensure zero breakout across 99.73 percent of panel sites. Relying on worst-case linear arithmetic over-designs land sizes, artificially constricting routing channels between microvias and driving up layer counts.

Microvia Capture Pad Clearance and Annular Ring Math

The relationship between microvia hole size, registration budget, and target land diameter governs the routing capacity of an HDI board. IPC-6012 Class 3 specifications require high-reliability electronics to maintain positive annular ring margins or limit microvia breakout to a maximum of 90 degrees, provided specified copper clearance to adjacent un-netted traces is preserved. Aerospace and medical hardware operating under Class 3/A rules permit no microvia breakout whatsoever, requiring the entire microvia perimeter to stay within the capture land.

IPC-6012 Class 3 performance standards mandate absolute zero microvia breakout on critical inner layers, forcing target lands to expand by double the statistical registration standard deviation.

The mathematical equation governing minimum target land diameter Dland to achieve zero microvia breakout under specified registration tolerances is expressed as:

Dland = Ddrill + 2 · RRSS + 2 · Aring

Where Ddrill is the nominal laser-drilled hole diameter, RRSS is the combined statistical registration error radius, and Aring is the minimum specified isolated annular ring margin (set to zero for Class 2 tangency, or 25 micrometers for Class 3 zero-breakout rules). Applying this formula to the calculated 3-sigma RSS registration value (RRSS = 54.26 μm) for a 100-micrometer laser microvia under Class 3 rules yields:

Dland = 100 + 2 · (54.26) + 2 · (25) = 100 + 108.52 + 50 = 258.52 μm

Meeting Class 3 zero-breakout requirements across three sequential lamination passes requires a minimum capture land diameter of 260 micrometers (10.2 mils) for a 100-micrometer (4 mil) laser microvia. Using a 200-micrometer pad on a 3+N+3 sequential build evaluated under Class 3 rules inevitably triggers heavy rejections during microsection inspection.

Where Do Microvia Target Offsets Exceed Annular Rings?

Microvia target offsets exceed annular ring allowances primarily at panel corners, where distance from the center (radial vector distance) amplifies linear scaling discrepancies. Because material expansion and rotational skew cause displacements proportional to distance from the panel neutral axis, microvias within 50 millimeters of the center show minimal registration error, landing almost dead-center on target pads. The same feature placed in the extreme corner of an 18-by-24-inch panel sees maximum vector shift, pushing the microvia off the capture land into dielectric space.

When target offsets breach the annular ring perimeter, three primary failure modes occur during bare-board processing:

• Dielectric Hole Wall Micro-Cracking during mechanical stress cycles due to uneven plating metal distribution across the exposed land interface.
• Conductive Anodic Filament (CAF) Growth pathways opening between the breakout copper wall and adjacent internal power or ground planes.
• Desmear Chemical Overshoot attacking the exposed resin interface around the pad edge, creating resin voids during electroless copper plating.

Unexpected resin lot variations can drive inner-layer core movement outside standard material slash-sheet parameters, contributing to microvia breakout defects.

Drill

X-Ray Inspection and Inner-Layer Target Optimization

To mitigate cumulative lamination errors, modern board processing uses intelligent X-ray target drilling before mechanical or laser drilling outer layers. Once a sequential lamination sub-assembly leaves the hydraulic press, internal alignment targets etched onto deep inner layers sit concealed beneath solid outer copper sheets. The panel moves through an automated X-ray system equipped with dual-axis imaging heads that locate the spatial coordinates of target pads buried four to twelve layers deep.

Rather than assuming the panel matches original CAD geometry, the X-ray target optimizer calculates a best-fit transformation matrix for that specific panel. The system compares actual X-ray coordinates of four or eight interior corner targets against design file locations to derive a correction matrix with independent x- and y-axis scaling, rotational offset, and origin translation. It then drills mechanical alignment holes using these optimized coordinates, keeping downstream drilling centered over the actual locations of internal target lands.

X-ray inspection provides crucial diagnostic data by measuring layer-to-layer offsets before downstream processing. If the system detects that inner layer 3 shifted 60 micrometers relative to layer 4 during lamination, it flags the panel for scrap or adjusts outer-layer laser parameters to split the error between the two layers. Distributing registration error across multi-layer interfaces prevents catastrophic breakout on critical nets while accepting minor alignment shifts on ground planes.

Dynamic Scaling Factors in Multi-Axis Drill Optimization

High-end laser drills use dynamic multi-axis field scaling to compensate for uneven substrate deformation across large panels. Older systems applied a single static scaling factor over the whole panel surface; if the laminate shrank by 200 PPM, the optics scaled the entire drill grid down by 200 PPM. Modern dynamic scaling divides the panel into localized zones or individual BGA footprints, scanning local X-ray or optical fiducials around each component area before drilling microvias in that zone.

Dynamic local scaling allows laser drills to adjust galvanometric mirror sweeps independently for each BGA array. If localized resin movement during lamination causes 350 PPM shrinkage in the top-right quadrant but only 120 PPM in the bottom-left, the machine updates its coordinate map as the drill head moves across the panel. This localized scaling drops effective laser registration error from +/- 25 micrometers down to +/- 8 micrometers, enabling tighter microvia pads within fine-pitch BGA arrays.

Implementing dynamic scaling requires dedicated local fiducials inside the active circuit area. Design rules mandate at least three optical fiducials around any BGA footprint with a pitch of 0.4 millimeters or smaller. Omitting these local markers forces the fabricator to fall back on global panel fiducials, losing the benefit of dynamic scale correction and raising microvia breakout risks beneath dense components.

Dielectric selection directly affects laser ablation depth accuracy. Variations in resin-to-glass ratios across a panel cause uneven beam absorption, producing microvia depth variations that degrade contact with target lands below.

Standard fabrication contracts govern layer registration through explicit baseline clauses. Under IPC-6012 Section 3.4.1, inner-layer registration is evaluated primarily via annular ring measurements on microsection coupons cut from panel margins. When microsection analysis shows microvia breakout beyond contractually agreed limits, the entire delivery lot is subject to rejection unless the buyer issued a written waiver granting Class 2 tangency before job release.

Margin

Yield Loss Curves per Sequential Lamination Pass

Every added lamination pass in an HDI stackup multiplies yield loss. Bare-board manufacturing yields compound across process steps. If a single lamination, imaging, etching, and drilling cycle achieves a 95 percent first-pass yield, running three sequential cycles reduces net stackup yield to 0.95 · 0.95 · 0.95 = 0.857, or 85.7 percent.

A fourth lamination pass for an ELIC build drops panel yield to 81.4 percent under identical process controls.

The cost of scrap rises sharply as a board moves through lamination stages. Defects at the first inner-layer etch stage waste only raw laminate core and copper foil. Scrap at the third lamination pass destroys a semi-finished assembly carrying multiple etched cores, buried via plating, specialized dielectric films, and hours of machine time.

Pricing for a 3+N+3 or 4+N+4 sequential build reflects these compounding scrap risks, driving finished panel costs far above standard 1+N+1 structures.

Designing for high yield means balancing microvia target land dimensions against process capability. Shrinking target lands from 250 micrometers to 200 micrometers on a 2+N+2 stackup might free up 20 percent more signal routing space, but if the fabricator’s process standard deviation is 15 micrometers, that change drops the process capability index (Cpk) from 1.33 to 0.88. Operating below 1.0 Cpk causes yield to fall sharply, forcing the plant to scrap dozens of panels to fulfill a single batch order.

Fabrication Drawing Notes That Protect Panel Yield

Engineering drawings form legal contracts between board buyers and fabricators. Ambiguous registration notes lead to disputes, rejected lots, or shop-floor modifications that compromise reliability. To avoid these issues, fabrication notes should state explicit registration parameters, IPC performance classes, microvia breakout rules, and material slash-sheet constraints.

A complete fabrication note suite for a sequential HDI stackup details explicit registration standards rather than relying on shop defaults. Drawings should state whether Class 2 or Class 3 registration applies to each layer interface, and specify if staggered microvias can replace stacked microvias. Staggered microvias ease registration demands and improve yield, though they alter routing impedance and spatial layouts.

Explicitly permitting staggered microvias on the drawing gives the plant flexibility to optimize registration margins without triggering engineering holds.

Fabrication drawings should also mandate sub-core pre-baking requirements and define acceptable artwork compensation methods. Explicitly calling out IPC-4101/126 or IPC-4101/131 materials ensures the plant uses high-stability, low-shrinkage substrates rather than cheaper substitutes with high directional anisotropy. Specifying slash sheets directly locks in material movement coefficients, tightening the error budget and protecting dense routing features.

Panel Utilization and Financial Penalties of Oversized Target Lands

While expanding microvia capture lands improves factory yields, oversizing target pads penalizes layout efficiency. Component density in modern electronics is governed by BGA pitch. A 0.5-millimeter BGA has a pad spacing of 500 micrometers center-to-center.

Placing a 250-micrometer target land within a 500-micrometer grid leaves 250 micrometers total clearance between adjacent lands. Subtracting solder mask dam clearances and trace-to-pad rules leaves no room to route an escape trace between adjacent BGA pins on that layer.

When target lands block routing between BGA pins, designers must drop via connections to deeper inner layers to complete signal escapes. This blockage forces extra signal layers and additional lamination cycles. Upgrading a stackup from 2+N+2 to 3+N+3 to accommodate oversized target lands increases panel manufacturing costs by 35 to 50 percent, while adding another high-risk press pass that depresses yield.

Panel utilization efficiency directly drives unit board pricing. Standard production panels measure 18 by 24 inches (457 by 610 mm) or 21 by 24 inches (533 by 610 mm). Outer perimeter margins of 20 to 35 millimeters are reserved for lamination pin holes, optical alignment targets, X-ray drill targets, thief bars, and test coupons.

This unusable border consumes up to 22 percent of panel area. If oversized target lands force a board outline to expand by just 5 millimeters, the array count on a standard panel can drop from 12 boards down to 8. That 33 percent reduction in panel yield drives up landed unit costs proportionally.

Calculating the true cost per square meter of finished HDI bare boards requires weighing fully burdened panel costs against net shippable boards. A 3+N+3 panel costing $1,200 across four lamination cycles that yields 10 good boards results in a base unit cost of $120. If microvia target lands are specified too tightly under Class 3 rules, causing registration yield to drop from 90 percent to 60 percent, shippable boards fall from 10 to 6 per panel.

The unit price jumps from $120 to $200 as fewer boards absorb the cost of registration scrap.