Registration Error Vectors in High Density Interconnect Stackups
Controlling HDI registration vectors demands balancing core dimensional shrinkage, LDI grid warping, and stackup symmetry to prevent microvia pad breakout.
Layer Overlay Accuracy
Vertical Alignment
Specifications for the alignment between conductive patterns on different layers of a printed circuit board define the structural integrity of the vertical interconnects. High layer overlay accuracy ensures that the annular rings on internal layers are centered around the drilled holes to prevent electrical failures or breakout. This metric is usually expressed as a distance representing the maximum deviation of any layer from its theoretical center.
Fabricators use specialized X-ray inspection systems to verify the positions of internal copper features after the lamination process is complete.
Fabrication Tolerance
Cumulative errors from film expansion and mechanical pin tolerances contribute to the total registration budget. Increasing layer overlay accuracy requires the use of high definition imaging systems and stable core materials. In complex multi-layer boards, the tolerance for this deviation is often less than 0.003 inches.
When the error exceeds the design limits, the drill may miss the internal pad or sever the connection to the plane. Advanced manufacturing facilities use laser direct imaging to eliminate the errors associated with physical phototools.
Destructive Testing
Physical verification of the alignment in a finished board relies on cross-sectional analysis. This test confirms that the layer overlay accuracy meets the requirements of standards such as IPC-6012.