Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Modified Counting Sequence
Pattern Generation
Algorithmic test vectors applied to digital circuits facilitate the detection of short-circuit faults between interconnected nodes. This diagnostic technique, referred to as a modified counting sequence, generates a series of binary patterns designed to identify solder bridges and open circuits on assembled boards. The generation process creates a set of test vectors where no two pins receive the same sequence, and no pin receives all zeros or all ones.
These constraints prevent false passes when pins are shorted to ground or power planes.
Test Execution
Executing the diagnostic routine involves driving the generated binary sequences onto the board-level netlist through boundary scan cells. During this test, a modified counting sequence applies the patterns to the input pins while capturing the resulting states on the corresponding output pins. The captured patterns are compared against the expected states to identify discrepancies.
By using a logarithmic progression of vectors, the routine keeps the total test time short while maintaining high fault coverage.
Diagnostic Action
Localization of specific defects relies on analyzing the pattern of failures returned by the test run. When a short circuit exists between two nets, both nets exhibit identical modified counting sequence signatures. The diagnosis algorithm identifies the shorted nets by matching these signatures, allowing repair technicians to locate the solder bridge on the assembly.
This testing procedure occurs during the post-reflow inspection phase to catch bridging defects before the boards are installed into final enclosures. By pinpointing the exact location of the defect, the test minimizes rework time and prevents the scrap of completed assemblies. In high-density assemblies where visual inspection is obstructed by ball grid array packages, this electrical localization represents the only reliable means to detect hidden solder bridges.