Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Netlist Fault Coverage
Test Effectiveness
Percentage metrics representing the proportion of modeled faults detected by a test pattern set determine the quality of a structural test program. This netlist fault coverage provides a quantitative measure of how thoroughly the test vectors can screen for physical defects on the board. A higher percentage directly corresponds to fewer defective units escaping to the customer.
Developing a test suite that maximizes this metric is a standard requirement in contract assembly. This validation ensures that the automated test vectors exercise every internal connection and logic gate on the fabricated board.
Structural Verification
Fault simulators analyze the gate-level design description to identify undetected circuit nodes. To calculate the netlist fault coverage, the simulator injects stuck-at or open-circuit faults into the netlist and runs the test patterns. Any node that remains unobservable after the test sequence represents a gap in test coverage.
Designers use these reports to add test points or scan registers to the schematics.
Coverage Optimization
Design complexity and test access determine the practical limit of achievable verification. If a board lacks scan chains or physical test points, the netlist fault coverage will be low because internal signals cannot be toggled or observed. Achieving a high coverage value requires structural design-for-test practices during the schematic stage.
This preemptive planning saves engineering time and prevents field failures.