Boundary Scan Interconnect Testing Essentials for Populated Circuit Board Assemblies
Boundary scan interconnect testing turns silicon multiplexers into virtual probes to verify fine-pitch BGA solder joints without physical test pads.
Open Joint Fault Model
Simulation Model
Mathematical representations used in electronic design automation software to simulate the electrical behavior of a disconnected solder joint between a component pin and a circuit board pad enable the automated generation of targeted test patterns. Incorporating an open joint fault model into the test development process allows test generation algorithms to create vectors that catch incomplete solder connections. This model replaces simplistic stuck-at fault models for pins that are left floating due to solder failure.
It ensures that the generated test patterns are highly effective at detecting real-world assembly errors. This diagnostic modeling forms the backbone of structural in-circuit testing for high-pin-count chips.
Electrical Behavior
An open solder joint results in a floating pin that behaves unpredictably due to capacitive coupling from neighboring signals. The model represents this behavior by calculating the potential voltage of the disconnected pin based on adjacent signal lines. Test patterns must be designed to hold these neighboring lines at a stable state to ensure the fault is detectable.
This modeling prevents the occurrence of intermittent test failures.
Fault Diagnostics
Automated test systems execute these models to diagnose failures to the exact pin location on the board. This diagnostic precision reduces manual rework time. Test operators quickly apply solder to the pin identified by the system.