Plating Density Equalization
Sacrificial metal structures added to printed circuit board manufacturing panels balance electrical current distribution during electroplating processes. A panel thieving pattern consists of isolated copper dots or grid arrays placed in blank panel areas to draw excess current away from isolated circuit traces. Boundaries of application remain within non-functional panel borders and unused board spaces, terminating at the final board profiling step.
Including these balancing features ensures uniform copper deposition thickness across all board features on a production panel.
Electroplating Dynamics Scheme
Electroplating bath dynamics cause high electrical field concentrations near isolated circuit traces and panel edges, resulting in uneven copper plating thickness. High current density zones experience excessive copper build-up, causing over-plated trace widths and out-of-tolerance plated hole diameters. Conversely, dense trace areas draw low local current, yielding thin copper walls in high-aspect-ratio vias.
Adding dummy copper shapes equalizes effective copper surface area across the entire panel area, distributing electrical lines of force uniformly during plating cycles. Etching processes also benefit from balanced copper density, preventing localized over-etching of fine signal lines adjacent to large copper isolation gaps. Automated computer-aided manufacturing software places copper thieving patterns automatically based on local copper density calculations prior to photo-tool generation.
Fabrication Acceptability Boundary
Unbalanced copper distribution without thieving patterns leads to board bowing and twisting during thermal exposure. Uniform plating thickness guarantees consistent controlled impedance values and reliable hole wall integrity across every board on the panel. Fabricators verify copper thickness uniformity using microsection coupons.
