Printed Circuit Assembly Test Point Access Guidelines
Test point geometry and access density directly dictate structural fault coverage, fixture expense, signal integrity, and field escape liabilities across production batches.
Parasitic Stub Capacitance
Capacitive Load
An unwanted reactive electrical property arises from unused conductive via barrels extending beyond the active signal routing layer in multi-layer printed circuit boards. In high-speed digital circuit design, parasitic stub capacitance adds unwanted capacitive loading to transmission lines, altering characteristic impedance and causing signal reflections at gigahertz frequencies. The capacitive impact stops affecting signal transmission when trace operating frequencies remain low enough that stub electrical length is negligible relative to signal wavelength.
Signal Degradation
Unterminated via stubs act as open-circuited transmission line segments connected in parallel with signal traces. At high frequencies, these copper stubs store electrical charge and create local impedance drops along the transmission path. Edge rate degradation and intersymbol interference worsen as signal frequencies increase toward the quarter-wave resonant frequency of the stub.
Discontinuities created by stub capacitance degrade eye diagram opening heights and increase jitter in multi-gigabit serial links. Circuit designers eliminate unwanted stub metal through controlled-depth backdrilling during printed circuit board fabrication. Removing the unused via segment restores uniform trace impedance and eliminates local capacitive loading across high-speed net transitions.
Electromagnetic field solvers calculate total stub capacitance to predict insertion loss profiles across target frequency bands.
Via Optimization
Backdrilling unrouted via portions reduces parasitic stub capacitance to maintain signal eye opening. Omitting stub removal causes bit error rate degradation in high speed serial channels.