Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Pin Level Fault Coverage
Quantified Inspection
The mathematical ratio of physically verifiable component lead connections against the total number of active component pins on an assembled printed circuit board measures structural test effectiveness. During automated in-circuit and boundary scan testing, pin level fault coverage quantifies the exact proportion of component leads screened for solder opens and short circuits. High coverage percentages confirm that manufacturing defects such as lifted leads and solder bridges are systematically detected.
Test program reports express this metric as a percentage of total component pin terminations on the assembly.
Boundary Verification
Achieving high coverage metrics requires individual probe contact or boundary scan access for every active pin on integrated circuits and discrete components. In pin level fault coverage evaluations, open solder joints on non-accessed pins reduce total coverage scores even if the overall electrical net remains partially functional. Boundary scan vectors test internal digital pin drivers and receivers without physical probe contact, elevating coverage on dense digital assemblies.
Unconnected pins, power plane connections and analog bypass pins require specific test classification rules to avoid inflating coverage calculations. Automated test generation software calculates fault coverage metrics by dividing detected pin faults by the total fault universe defined in CAD netlist data. Solder joint defects hidden beneath large ball grid array packages represent the primary cause of reduced coverage scores when physical probing is restricted.
Quality Bounds
Complementary inspection technologies improve overall defect detection when physical test pad placement is limited by board space. Automated X-ray inspection targets unprobed pin locations to maintain high defect detection confidence across complex assemblies. Test specifications mandate minimum pin coverage thresholds prior to approving boards for commercial volume production.