Inner Layer Alignment Metrics under Anisotropic Thermal Lamination Shrinkage
Anisotropic inner layer shrink requires asymmetric artwork scaling factors matching prepreg warp and fill glass weave thermal coefficients.
Pin Line Clearance
Hole Spacing
Physical separation between the outer edge of a plated through hole and the copper circuitry of an adjacent conductive pad determines the pin line clearance. This measurement prevents inadvertent electrical shorts caused by copper migration or drilling inaccuracies during the fabrication process. Manufacturers calculate the distance by subtracting the hole radius and the surrounding annular ring from the nearest trace edge.
Maintaining the required gap ensures reliable connectivity while minimizing risk during the subsequent assembly stage.
Registration Tolerance
Drilling alignment shifts or lamination movement during board manufacture reduce the pin line clearance beyond design specifications. Mechanical drill bits often deflect upon contact with glass fibers within the resin, creating non-concentric holes that encroach upon restricted zones. Designers verify these margins through automated optical inspection equipment capable of detecting subtle deviations in conductive geometry.
Strict control over layer registration throughout lamination and drilling cycles keeps these values within the tolerances defined by the IPC 6012 standard.
Electrical Integrity
Voltage breakdown thresholds in high density interconnects depend on the pin line clearance to manage the dielectric strength of the insulating substrate. Contamination or moisture trapped in tight spaces degrades the local insulation resistance and promotes dendrite growth under bias. Tight geometric controls permit smaller board footprints without sacrificing the signal quality or long term reliability of the finished assembly.
Higher spacing requirements reflect the specific needs of high voltage applications where arc tracking constitutes a failure mode.