Geometric Aberration
Lateral displacement within a fabricated circuit board substrate marks a plane discontinuity. This structural separation occurs when internal copper layers or dielectric cores shift during the high heat and pressure cycles of lamination. It defines a breakdown in the expected alignment of vertical interconnects, potentially severing the conductive path between layers or reducing the insulation barrier.
The defect limit resides at the point where the shift forces an annular ring width below the minimum requirements set for reliable signal transition or dielectric withstand voltage.
Fabrication Tolerance
Registration errors in multilayer press systems trigger this displacement. Automated optical inspection tools detect these misalignments by comparing the actual position of drilled holes against the intended pad center points on inner layers. When the measured offset exceeds the allowable design margin, the board fails the inspection criteria.
Such conditions introduce impedance variations, as the altered geometry changes the local capacitance and inductance between signal traces and reference planes.
Structural Outcome
Mechanical stress during lamination or material expansion differences between resin and glass fibres drives these layer drifts. Board assemblers identify these inconsistencies through cross-section analysis, verifying if the physical reality matches the design file output. Consistent failure at this stage signals a need to adjust tooling pins or press profiles to prevent thermal drift.
A verified absence of this misalignment guarantees that the electrical integrity remains stable throughout the life of the component.
