Layer Specification
Engineering drawing instructions define the mechanical sequence, copper weights, dielectric thicknesses, and manufacturing tolerances required to construct a multilayer printed circuit board. Circuit layout authorities provide stackup fabrication notes to govern foil selections, prepreg types, and target impedance values at incoming fabrication processing. The authority of these instructions halts where standard shop practices govern non-critical panelization and tooling borders.
Dielectric Sequencing
Stackup drawing notes explicitly assign base material types, dielectric classifications, and layer build orders to achieve target electrical performance. When controlled impedance traces require specific dielectric spacings, the instructions define target line widths, reference plane assignments, and allowable impedance tolerances. The documentation instructs fabricators on whether specified dielectric dimensions represent pressed thicknesses or unpressed core values.
Notes also define copper foil treatment types, foil profiles, and surface finish requirements on external layers. Fabricators review these instructions during engineering query stages to reconcile designer stackups with stocked laminate sheet thicknesses. Clear instructions prevent unauthorized material substitutions that could alter high-frequency propagation, thermal expansion behavior, or assembly reflow survivability.
Quality Conformance
Incoming quality assurance audits finished panel cross-sections against the approved stackup drawing. Fabrication test coupons verify that controlled impedance lines fall within the specified percentage window. Contradictory or missing instructions cause manufacturing delays, incorrect prepreg selections, and batch rejections.
Defensible stackup documentation forms the legal technical baseline for board acceptance and fabrication compliance.