Temporal Offset
Temporal offsets between paired conductors on internal circuit layers arise from local differences in the surrounding dielectric environment. High speed designs encounter stripline differential skew when the two traces of a pair travel over different portions of the glass weave. This mismatch in arrival time converts the intended differential signal into a common-mode signal, leading to increased electromagnetic emissions and reduced noise immunity.
Fiber Weave
Woven glass fabrics used in PCB cores are not homogeneous. Because the dielectric constant of the glass is higher than that of the resin, the signal speed depends on the amount of glass immediately surrounding the trace. Stripline differential skew is particularly difficult to manage because the traces are completely embedded between two glass-reinforced layers.
If one trace is aligned with a glass yarn while its partner is aligned with a resin gap, the resulting speed difference can reach several picoseconds per inch. This effect becomes a limiting factor for high speed interfaces like PCIe or 100G Ethernet where timing budgets are very tight.
Jitter Constraint
Signal integrity at the receiver is degraded by the closing of the eye diagram caused by timing errors. Stripline differential skew adds to the total jitter of the system, making it harder to recover the clock and data. To control this, manufacturers may use spread-weave fabrics or route the traces at an angle to the glass bundles.
Verification is performed by measuring the phase difference between the two conductors using a vector network analyzer or a high speed sampling oscilloscope.
