Deriving Boundary Scan Diagnostic Coverage for High Density ASIC Arrays
Deriving boundary scan coverage for high-density ASIC arrays requires precise accounting of scannable versus un-scannable nets to prevent costly field escapes.
Stuck-at Fault Model
Fault Logic
Logical simulation operates on gate-level netlists to predict observable responses for predefined circuit defects during board manufacturing. The stuck-at fault model assumes that a given signal line inside a printed circuit board assembly is permanently tied to a fixed binary voltage level. Test engineers apply this abstraction during automated test pattern generation to target permanent bridging errors and internal open circuits arising from faulty reflow soldering.
Physical defects that bridge a trace directly to ground or power supply rails produce a permanent logic zero or logic one state during digital verification.
Test Generation
Algorithms evaluate millions of potential pathways through combinational logic blocks to isolate test vectors that expose hidden net failures. Boundary scan architectures exercise internal nodes through standardized test access ports when physical probe access is restricted by high component density. Manufacturers measure vector efficiency by calculating the ratio of detected faults against the total modeled fault universe.
Defect Coverage
Diagnostic routines separate manufacturing assembly defects from underlying silicon fabrication flaws by analyzing the specific propagation paths of failed test vectors. Automated optical inspection catches bridging bridges before electrical power reaches the board, while functional verification catches the behavioral anomalies predicted by logical abstractions. Board assemblies leaving the production line achieve target defect levels when test vectors exercise every accessible node through strict logic constraints.