Sequential Lamination Registration Budgets across High Density Interconnect Stackups
Sequential lamination registration budgets require root-sum-square alignment modeling of sub-core thermal shrinkage and drill offsets to size microvia lands.
Sub-Core Scaling
Multi-Layer Alignment
Adjustment of inner-layer circuit patterns compensates for the material expansion and contraction that occurs during the multi-layer lamination process. This pre-compensation technique, termed sub-core scaling, involves resizing the artwork before the layers are etched and assembled. Without this modification, the cumulative shifting of thin laminates under heat and pressure would cause severe drill-to-pad misalignment, causing board failures.
Mathematical Compensation
Fabricators calculate the required scaling factors using empirical data gathered from previous production runs of similar material stack-ups and thicknesses. These factors are applied to the photolithography tools to stretch or shrink the trace artwork along the x and y axes. When the laminate core subsequently expands or contracts during lamination, it returns to the desired nominal dimensions, ensuring the copper pads align perfectly with the drill pattern.
Because each dielectric material has a unique shrinkage rate, scaling factors must be customized for each material supplier and layer thickness.
Registration Verification
High-precision manufacturing environments use post-lamination X-ray systems to scan the inner layers and evaluate the effectiveness of the scaling. This analysis allows engineers to refine the scaling coefficients for future production batches of the same material. Consistent scaling represents the primary method for maintaining registration in high-density interconnect designs.