Routing Interface
Thin-film metal and dielectric levels reposition the fine-pitch contact points of a semiconductor die to the wider spacing of a package carrier. A substrate redistribution layer enables the connection of high-density integrated circuits to standard printed circuit boards. It consists of copper traces deposited onto a passivation surface.
This structure manages the transition between micro-scale and macro-scale electronics.
Fan-Out Architecture
Creating a substrate redistribution layer involves photolithography and plating processes similar to those used in wafer fabrication. The traces route signals from the crowded center of a chip to the peripheral bond pads or solder balls. By increasing the available area for interconnects, this layer supports higher input and output counts.
Dielectric materials must possess low loss tangents to maintain signal integrity at high frequencies. Stress buffers prevent the die from cracking during the curing of the organic layers. Multi-layer designs allow for complex power and ground plane configurations within the package itself.
Manufacturing Precision
Tight tolerances on trace width and spacing are required to prevent electrical shorts. Inspection of the substrate redistribution layer occurs before die attachment to maximize final assembly yield. Laser direct imaging often provides the necessary resolution.
High-quality layers ensure reliable electrical paths.
