Power Plane Eddy Current Attenuation and Stitching via Parasitics in High Speed Substrates
Stitching via arrays and eddy current losses damp cavity resonances to suppress power plane noise in high-speed substrates.
Surface Roughness Loss
Conductor Loss
High frequency attenuation increases along printed circuit board traces due to prolonged current paths caused by micro-profile tooth variations on copper foil surfaces. Microwave and high speed signal engineers calculate surface roughness loss during channel loss modeling and TDR testing. This attenuation mechanism excludes dielectric dissipation factor losses inherent to substrate resin materials.
Skin Attenuation
High frequency alternating currents crowd near the outer surface of conductors due to skin effect physics, reducing effective current carrying cross-section. When conductor copper foils feature rough surface profiles designed to enhance mechanical adhesion to dielectric prepreg, high frequency currents must travel up and down the microscopic copper peaks. This elongated physical path increases effective trace resistance and causes severe surface roughness loss at multi-gigahertz frequencies.
Electro-deposited copper foils exhibit higher surface profile peaks than low-profile rolled-annealed foils, creating greater insertion loss along identical route lengths. Vector network analyzers measure S-parameters to quantify total insertion loss and isolate conductor loss components from dielectric absorption. Chemical treatment steps during lamination alter copper topography, requiring precise process control to balance bond strength with high speed signal performance.
Substrate Roughness
Smooth copper foil profiles reduce high frequency signal attenuation on long PCB traces. Sacrificing profile height lowers conductor loss while requiring specialized adhesion promoters. Accurate insertion loss modeling incorporates measured copper surface profile metrics.