Data Ingest
Serial input pins on a boundary scan chip receive test vectors and instructions from the automated test equipment. The test program uses the tdi pin to load logical states into the boundary scan register one bit at a time. This line is sampled on the rising edge of the test clock by the internal test access port logic.
This provides the primary path for controlling pin states during board-level diagnostic routines.
Routing Architecture
Connecting multiple JTAG-compliant chips on a board in a daisy-chain configuration connects the output of one device to the input of the next. The system board routing connects the primary tdi line from the test header to the first chip in the chain. Data is shifted sequentially through every device before reaching the final output pin of the board.
This chain configuration simplifies the physical trace routing of the board by using a single serial path, which saves valuable board area on high-density assemblies.
Signal Protection
High reliability on the factory floor requires that this high-speed clock-synchronized signal is protected from electromagnetic noise and crosstalk. Long scan-chain traces must be routed with proper pull-up resistors to prevent floating logic states when the test probe is disconnected. Testing this line for signal integrity ensures that diagnostic patterns are loaded without corruption during assembly verification.
