Quantifying Structural Netlist Coverage Limitations Using Standard IEEE Boundary Scan Protocols
Boundary scan netlist coverage is bounded by physical TAP access, requiring explicit fault universe math to quantify unverified structural escape risks.
Serial Scan Chain
Register Routing
Linking shift registers sequentially in a digital chip allows parallel internal data to be shifted out through a single test pin. Board-level boundary scan uses a serial scan chain to route test data through multiple active components in a single path. This path begins at the test data input pin and flows sequentially through each boundary scan cell to the test data output pin.
This minimizes the physical board space required for test access by using only four or five dedicated pins.
Vector Propagation
Shifting patterns through the linked registers sets the logical state of every connected device pin simultaneously. The scan operation runs under the control of the test clock, moving one bit per clock cycle through the entire sequence of registers. Once the test vectors are shifted in, the device captures the parallel inputs and shifts them out for evaluation.
This mechanism allows deep internal logic states to be tested without using external physical test probes, and it works independently of the functional firmware of the board.
Structural Diagnostic
Discrepancies in the returned data stream show the exact location of open circuits or solder shorts between the components. If a register in the sequence fails to pass data, the test system immediately localizes the break in the path. This provides board-level diagnostics that can find a single broken solder joint under a high-pin-count device.