Spatial Tolerance
Dimensional precision in the spacing between adjacent conductive paths on a printed circuit board is required to prevent electrical shorting and maintain signal characteristics. This relative positioning, referred to as trace pitch alignment, must be held to tight tolerances during the imaging and etching stages of board fabrication. The alignment ensures that the physical center-to-center distances between traces remain uniform across the entire board surface.
It defines the limits for signal trace placement in dense multi-layer boards.
Lamination Registration
Multi-layer board fabrication requires the precise stacking and lamination of individual double-sided circuit layers. During this process, trace pitch alignment is maintained by using registration pins and optical alignment marks to align the layers before they are pressed together. If the layers shift during lamination, the copper traces on different layers will fail to align with the drilled through-holes.
This shift causes pad breakout and open circuits during subsequent plating processes.
Inspection Verification
Fabricators use automated optical inspection and X-ray systems to verify the spatial tolerances after lamination is complete. These inspection tools measure the relative position of the test structures on the board edge to confirm that the trace pitch alignment lies within the specified limits. If the measured drift exceeds the tolerance, the board is rejected to prevent internal short circuits or signal impedance variations.
This verification step is completed before drilling and plating to avoid the cost of processing defective laminate sheets. In high-density interconnect designs, this inspection represents the primary checkpoint for layer registration quality. The measured data is also used to adjust the imaging artwork for subsequent production runs to compensate for the dynamic shrinkage of the laminate during the lamination cycle.