Testing Protocol
Automated testing protocols verify the electrical functionality of individual semiconductor dies while they remain in a wafer format. Manufacturers use wafer level probing to identify defective components before the expensive dicing and packaging stages occur. This procedure involves a precision probe card that makes temporary electrical contact with the bond pads or bumps on the surface of the wafer.
Process Efficiency
Testing at the wafer level significantly reduces the cost of failure by preventing the assembly of bad dies into finished packages. During wafer level probing, a prober station moves the wafer with sub-micron accuracy to ensure that the probe needles land correctly on each die. The system runs a series of DC and high frequency tests to check for shorts, opens, and performance specifications.
This data is used to create a wafer map, which guides the pick-and-place machines in selecting only the known-good dies for the next production step. Advanced probing systems can test multiple dies simultaneously to increase the throughput of the factory.
Yield Analysis
Statistical data gathered during the test provides a clear view of the manufacturing quality of the silicon. When wafer level probing reveals a cluster of failures in a specific area, engineers can trace the issue back to a particular step in the fabrication process. This feedback loop is necessary for optimizing the yield and reducing the overall production time.
The testing process also allows for the sorting of dies into different performance bins based on their speed and power consumption.
