Acceptance Metric
Manufacturing efficiency in printed circuit board fabrication measures the ratio of usable, defect-free unpopulated boards passing final electrical test relative to the total number of individual units launched into production. Fabrication shops calculate bare board yield after automated optical inspection and flying probe continuity testing isolate short circuits and dielectric breakdown flaws prior to component loading. High-density interconnect designs with narrow trace widths exhibit lower baseline values due to increased exposure to registration misalignments.
The metric excludes downstream assembly defects, bounding its focus strictly to substrate processing steps like etching and lamination.
Defect Dynamic
Inner-layer misalignment during multi-layer lamination creates systematic shorts that destroy entire production panels before outer-layer processing even begins. Solder mask bleed into surface-mount pads and microvia plating voids represent localized failures that degrade bare board yield across individual board positions. When etch chemistries drift past acceptable copper concentration limits, trace widths narrow unexpectedly, triggering immediate resistance failures during flying probe verification.
Process control systems monitor chemical baths continuously to prevent bulk scrap events.
Cost Consequence
Low production yields force fabricators to launch excess panel volumes to satisfy purchase order quantities. Panel scrap drives raw material losses and consumes capacity without generating billable product.
