Geometric Tolerance
Planarity deviation in printed circuit boards represents a structural departure from a flat plane that affects both bare board handling and subsequent component attachment. The presence of board warp distortion occurs during laminate manufacturing or high temperature processing, where asymmetrical copper distribution and thermal expansion differences between substrate layers induce mechanical stress. This physical deflection is constrained by industry standards to prevent downstream assembly failure, typically setting a maximum allowable limit of 0.75 percent for boards with surface mount components.
Assembly Impact
Mechanical instability during solder paste printing leads to uneven deposit heights and subsequent soldering defects. When board warp distortion exceeds allowable limits during the reflow stage, the coplanarity of fine pitch devices is compromised because the contacts cannot reach the warped solder pads. This separation leads to open circuits or weak solder joints on the elevated sections, while the depressed sections can experience solder bridging.
Double sided assembly exacerbates this issue since the first pass reflow increases the internal stress of the laminate. High thermal exposure during second side reflow can cause the board to flex further, creating unpredictable component alignment issues that cannot be easily corrected by manual reworking.
Measurement Method
Industry testing determines planarity deviation by resting the board on a precision surface plate with the concave side facing down. Inspectors measure the maximum vertical gap between the surface plate and the board surface using a dial indicator or a thickness gauge. This manual check is often replaced in high volume production by automated optical systems that map the surface height profiles of each board across a grid.
These automated scanners calculate the deviation across the diagonal to confirm the substrate complies with IPC TM 650 requirements before assembly begins.