Planar Tolerance
Surface planarity defines the vertical deviation of package lead tips from a single seating plane during surface mount technology assembly. Component co-planarity controls lead elevation variations across integrated circuits before solder reflow occurs on printed circuit boards. Laser optical inspection systems measure this physical offset to prevent open circuits caused by inadequate paste contact.
Manufacturing limits apply strictly to passive and active packaged devices prior to board insertion.
Alignment Margin
Automated pick and head machinery relies on precise lead geometry to deposit terminals accurately into printed solder paste volumes. Excessive vertical spread prevents proper wetting dynamics during thermal reflow cycles. Thermal expansion mismatches between silicon dies and organic substrates worsen original geometric variances.
Optical sensors capture 3d profiles of incoming hardware to reject warped gull wing leads before placement. Machine vision algorithms compute maximum allowable deviations from baseline reference coordinates.
Defect Threshold
Solder joint integrity depends entirely on absolute physical contact between terminal surfaces and board pads during heating stages. Uncontrolled package warping induces bridging defects or lifted leads during high speed production runs. Assembly lines reject lots exceeding strict micron limits to guarantee structural reliability over operating lifespans.