Dimensional Allowance
Permissible physical deviations from nominal design dimensions define the acceptable manufacturing boundaries for printed circuit board fabrication. Engineering drawings specify nominal copper track widths, hole diameters, and dielectric layer thicknesses along with their allowable upper and lower limits. The permitted variance across these physical dimensions constitutes the fabrication tolerance.
Manufacturing limits govern bare board production lines, setting criteria for etching accuracy and layer registration. The allowance stops applying once the bare circuit board passes into surface mount component assembly operations.
Etch Variation
Chemical etching processes naturally alter conductor geometries away from ideal rectangular cross-sections toward trapezoidal shapes. Over-etching reduces trace widths, increasing high-frequency conductor resistance and elevating trace characteristic impedance. Under-etching leaves excess copper, narrowing the spacing between adjacent conductors and increasing crosstalk coupling.
Fabricators apply etching compensation factors to photolithography artwork to ensure finished features stay within designated drawing tolerances. Mechanical drilling processes introduce hole location wander and drill run-out, which consume allowable annular ring margins around plated via holes. Solder mask registration variances must stay within bounds to avoid exposing adjacent copper tracks to solder bridges.
Acceptance Boundary
Quality inspectors verify board compliance against IPC-6012 class performance requirements using automated optical inspection and microsection cross-sectioning. Dimensional measurements confirm that finished track widths remain within ten percent of design values. Cross-section verification proves that plated barrel copper thicknesses satisfy minimum wall requirements across all through-holes.
Boards exceeding dimensional boundaries face immediate scrap rejection or engineering concession review. Controlled impedance traces undergo coupon testing on automated time-domain reflectometers before lot acceptance.