Layer Arrangement
High density interconnect structures utilize microvias and thin dielectric materials to increase the routing density per unit area of a printed circuit board. These hdi stackups facilitate the integration of fine-pitch components by allowing signals to transition between adjacent layers without the space constraints of traditional through-hole vias. The design involves sequential lamination steps where sub-assemblies are built and bonded to create a complex vertical network.
Fabrication Sequence
Manufacturing starts with a core layer that provides structural rigidity and initial routing paths. Laser drilling creates microvias that connect the core to subsequent buildup layers, which are added in cycles of foil lamination and etching. Each iteration of the process adds cost and complexity while reducing the available thermal budget for the board.
Proper registration of these layers is necessary for maintaining the electrical path between the tiny pads. Engineers often specify hdi stackups like 1+n+1 or 2+n+2 to describe the number of buildup layers added to each side of the core. These configurations allow for extremely small trace widths and clearances, supporting the high pin counts of modern processors and memory modules.
Material Constraint
Thermal expansion coefficients of the different resins and copper layers must be matched to prevent delamination during assembly. As the layer count increases, the risk of cumulative warpage grows. These hdi stackups reach their functional limit when the aspect ratio of the microvias exceeds the plating capability of the chemistry.
