Reflection Origin
Variations in characteristic transmission line impedance along a signal route cause partial reflection of high frequency electrical energy back toward the transmitter. High speed board designers and test engineers analyze impedance mismatch during time-domain reflectometry and signal integrity testing. This phenomenon excludes low frequency resistance changes caused by DC conductor temperature variations.
Discontinuity Profile
Uniform trace width, copper thickness and dielectric spacing establish constant characteristic impedance along a printed circuit board route. When a trace transitions across layer vias, component solder pads or trace geometry changes, impedance mismatch occurs at the boundary point. Transmitted high speed signal edges split into forward-propagating signals and reflected voltage waves that travel back along the conductor.
Reflected waves interfere with subsequent signal pulses, causing ringing, overshoot and eye diagram degradation at the receiving integrated circuit pad. Time-domain reflectometers send steep voltage steps down the trace and measure reflected voltage amplitudes to map impedance variations along the physical path length. Manufacturing tolerances in dielectric thickness or resin content cause trace impedance variations that exceed specified target boundaries.
Tolerance Limit
Controlled impedance design requires tight tolerances on laminate permittivity and copper trace etching. Mismatches degrade high speed data integrity and increase bit error rates. TDR testing confirms trace impedance remains within target tolerance bands.
