Modeling Dynamic Parasitic Loading Effects on Scan Network Timing Margins
Dynamic parasitic extraction during ATPG shift prevents false timing violations by accounting for state-dependent capacitance and power rail collapses.
Launch off Shift
Clocking Strategy
Transition fault testing techniques utilize the final clock pulse of the scan shift cycle to initiate a logic change before capturing the result. The launch off shift method is known for producing high fault coverage with relatively simple pattern generation compared to other delay test styles. This approach uses the scan enable signal to control the transition, which requires the signal to switch very quickly.
Signal Timing
Operation starts with the serial shifting of data into the scan registers at the standard test clock rate. In a launch off shift sequence, the last shift pulse serves as the launch event, and the capture pulse follows immediately after the scan enable signal is de-asserted. The primary challenge involves the distribution of the scan enable signal, which must reach every flip-flop on the chip simultaneously.
If the signal is too slow, the circuit will fail to capture the correct transition, leading to false failures. Physical design teams use high-speed clock trees to route these control lines.
Testing Tradeoff
Speed of the test depends on the ability of the hardware to support fast switching of the control lines. While launch off shift simplifies the generation of test vectors, it places a burden on the physical design of the scan enable network. Engineers evaluate the trade-off between the ease of pattern creation and the complexity of the routing required to support this testing mode.