Core Allowance
Maximum registration offset limits the allowable planar deviation between internal and external conductors during printed circuit board fabrication. This dimensional envelope governs core-to-core alignment tolerances across multilayer boards before outer layer imaging occurs. Thermal pressing cycles cause material expansion in epoxy glass laminates, which introduces systematic positional errors that require strict spatial containment.
Automated optical inspection equipment measures conductor centers against golden board coordinates to detect out-of-tolerance movement prior to outer layer etching. Photolithography exposure tools then apply localized scaling compensations to neutralize measured linear distortion across individual panels.
Shift Allowance
Conductor displacement limits dictate acceptable registration variances during sequential layer lamination and subsequent laser drilling operations. Mechanical drill wander compounds positional errors already present from core movement, which demands precise alignment budgets to prevent breakout conditions at via landing pads. X-ray inspection systems verify sub-surface feature placement by targeting embedded alignment targets within unpopulated panel blanks.
Micro-section analysis validates copper barrel centering inside plated through holes to confirm that positional shifts remain inside permitted boundaries.
Variance Control
Multi-layer registration limits constrain cumulative dimensional discrepancies that arise from successive wet chemical processing steps and elevated press temperatures. Material shrinkage varies with fiber orientation and copper distribution density across opposite panel faces, creating asymmetric distortion vectors. Pre-preg material selection and foil balancing minimize dimensional instability during high temperature bonding cycles.
Board shops apply predictive scaling factors based on historical lot data to compensate for known shrinkage patterns before artwork generation begins.
