Geometric Misalignment
Positional discrepancies between conductive patterns on different inner layers of a multi-layer board cause geometric offsets after lamination. Tooling pin tolerances, material thermal expansion, and press shrinkage cause copper features to shift away from true nominal positions. The planar offset between corresponding features across internal conductive planes is layer misregistration.
This defect parameter governs multilayer lamination accuracy and drill registration margins. The measurement applies strictly to relative offsets among layered conductive traces and drilled through-holes.
Annular Breach
Severe registration offsets push drilled via holes outside the perimeter of internal copper capture pads. When a mechanical drill bit strikes a shifted inner layer, the hole can sever the copper pad border, creating a breakout condition. This annular ring breakout reduces interconnect contact area, which promotes open circuits, thermal cycle cracking, and conductive anodic filament growth.
High-density interconnect boards with microvias require precise layer alignment to prevent blind vias from missing internal target landing pads. Fabricators apply optical pinless alignment systems and x-ray drill optimization to compensate for non-linear material movement during high-temperature lamination.
Inspection Criteria
Real-time x-ray inspection systems verify layer alignment accuracy by scanning sacrificial registration targets embedded in panel borders. Microsection cross-sections cut through via barrels reveal remaining annular ring widths to confirm compliance with IPC-6012 Class 3 requirements. Automated optical inspection verifies inner layer artwork prior to bonding, preventing pre-lamination positional errors from reaching the press.
Multi-layer panels exceeding allowable misregistration limits are rejected before drilling and plating operations consume further manufacturing costs.