Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Scan Chain Access
Interface Architecture
Internal shift registers integrated into silicon devices provide a pathway for executing digital test routines on assembled circuit boards. This testing capability, known as scan chain access, utilizes dedicated test pins to shift test patterns into internal registers and capture the resulting responses. By linking the registers of multiple integrated circuits into a single serial path, the system can bypass the physical limitations of mechanical test probes.
This interface establishes a standard method for testing highly dense digital assemblies.
Boundary Execution
Test execution begins by configuring the device pins into their test modes to control the internal flip-flops. When scan chain access is initiated, the test processor drives the test clock and test data input signals to shift serial patterns through each device in the chain. These patterns are shifted in one bit at a time until the registers are fully loaded with the test vectors.
Once the registers are loaded, the system triggers the system clock to capture the state of the surrounding board traces.
Board Diagnostics
Analyzing the captured data patterns enables the localization of opens and shorts between components. Discrepancies between the expected and captured test patterns indicate electrical faults in the signal paths between the integrated circuits. By tracing the shifted-out bits back to their physical pin assignments, scan chain access allows diagnostics to isolate the failing trace on the assembled board.
This testing represents a standard procedure during board debugging and return-merchandise authorization. In cases where components are placed in tight grids, this serial access provides the primary window into the circuit’s electrical performance. The diagnostic software generates a report that highlights the specific pins involved in the failure, which speeds up the rework process by directing technicians to the exact solder joint that requires repair.