IEEE Boundary Scan Architecture and Boundary Cell Selection Basics
Selecting boundary cells matching pin drive requirements enables full interconnect fault coverage and prevents system logic corruption during shift sequences.
TMS
Internal Control
Digital access logic in standard IEEE 1149.1 compliant devices uses a single control input signal to navigate the sixteen-state TAP controller state machine. TMS determines state transitions at every rising edge of the test clock line. Serial control sequences sent over this signal dictate whether the test logic enters capture, shift, update, or reset states.
Execution Sequences
Execution of structural test vectors across populated printed circuit board assemblies depends on synchronized state control inside every boundary scan device on the chain. Logic levels present on TMS during test clock transitions move the internal state controller through instruction and data register branches. Pull-up resistors on this line maintain a high logic state when the test interface is disconnected, forcing the TAP controller into the safe Test-Logic-Reset state after five clock pulses.
Noise or voltage droop on the control trace causes state controllers in downstream devices to desynchronize from the master boundary scan tester. Desynchronization halts test vector execution and risks driving unintended logic levels onto active system buses, potential driving high current contention between integrated circuits.
Automated Simulation
Automated test vector development tools simulate state machine traversal along the control line to verify test vector timing before deployment to production. Loss of signal integrity on TMS invalidates test results and prevents successful component programming over JTAG interfaces.