IEEE Boundary Scan Architecture and Boundary Cell Selection Basics
Selecting boundary cells matching pin drive requirements enables full interconnect fault coverage and prevents system logic corruption during shift sequences.
TRST
Optional Initialization
Hardware signals defined in IEEE 1149.1 boundary scan specifications provide asynchronous initialization of internal test access port state controllers. TRST forces the test logic directly into the Test-Logic-Reset state without requiring clock transitions on the test clock line. Active-low signals on this line ensure system logic remains unaffected by test circuitry during normal power-up.
Board-level Integration
Board-level testing and system initialization demand reliable power-on states to prevent boundary scan logic from accidentally asserting control over functional pins. When implemented on an integrated circuit, TRST provides immediate hardware reset capability for the TAP controller upon power application or system assertion. Pull-down or pull-up circuit design rules require holding this pin in its active low state during normal board operation, preventing electrical noise from switching the chip into boundary scan test modes.
Floating reset pins lead to sporadic TAP controller activation, causing transient output bus tri-stating or logic state corruption on active system traces. Production functional testing asserts this signal between boundary scan runs to guarantee that all shift and update latches release control back to functional system logic.
Qualification Testing
Qualification testing for high-reliability military and automotive electronics mandates verification of active-low reset response times. Inadequate noise filtering on TRST causes unexpected boundary scan resets during active component programming cycles.