Vertical Clearance
Vertical stackup error allocation accounts for the cumulative variations in material thickness and manufacturing steps during circuit board fabrication. Calculating a z axis tolerance budget ensures that internal vias align with signal layers and that the final board thickness fits within its enclosure or connector. The budget includes variables such as prepreg compression, core thickness deviation, plating thickness and copper foil profile.
Engineers use these calculations to set the drill depths and lamination parameters.
Cumulative Error
Variation analysis combines the tolerances of each individual layer to determine the worst-case thickness of the finished assembly. A z axis tolerance budget must account for the fact that not all layers will be at their maximum or minimum thickness simultaneously. Statistical modeling is often used to predict the actual distribution of thicknesses in a production lot.
If this budget is exceeded, the board may be too thick for its housing or too thin for a press-fit connector to seat properly.
Assembly Clearance
Component height describes the space available between the top of the circuit board and the nearest mechanical obstruction. The z axis tolerance budget includes the height of the surface-mount components and the thickness of the solder joints. Proper allocation of these tolerances prevents interference between the board and the product case.
This calculation is a required step in the mechanical design of high-density electronic products.