Quantifying Structural Netlist Coverage Limitations Using Standard IEEE Boundary Scan Protocols
Boundary scan netlist coverage is bounded by physical TAP access, requiring explicit fault universe math to quantify unverified structural escape risks.
ATPG
Pattern Generation
Electronic design automation software algorithms that produce binary stimuli to detect structural defects in manufactured integrated circuits establish the foundation for post-fabrication quality control. Applying atpg during the design phase generates vectors that target internal flip-flops and logic gates. The resulting vectors are loaded into automatic test equipment to identify physical faults.
This automated process replaces manual test writing and decreases production test time. By analyzing the netlist, the generation engine optimizes the pattern count to minimize tester memory usage and test execution cost.
Fault Coverage
Design for testability rules require the insertion of scan chains to make internal nodes observable to the generation software. The algorithm models stuck-at faults and transition delay faults to measure the thoroughness of the vector set. Low coverage indicates unobservable paths that might harbor assembly or fabrication defects.
Designers revise the scan structure when the coverage percentage falls below the specified quality threshold.
Assembly Application
Physical board-level tests use the generated vectors to verify that soldered chip pins are fully connected to the circuit board. Solder voids or broken joints block the test pattern and trigger a scan failure on the tester. This diagnostic output pinpointing the failing pin simplifies manual rework.
Boards with higher test coverage suffer fewer field failures.