Defect Modeling
Logic nodes locked permanently to a high or low voltage level regardless of the input conditions represent a common failure mode in digital boards. Circuit diagnostics use the stuck-at fault model to represent physical defects such as solder shorts to ground or open signal lines. The model assumes a net is either fixed at logic one or logic zero.
This simplification allows test software to generate efficient vectors that check every node on the board.
Diagnostic Method
Test patterns are calculated to force the opposite state onto the target node and observe the output to see if it changes. If the board node is stuck, the expected transition does not occur, and the tester flags a failure. Solder bridges to the ground plane will cause a stuck-at-zero defect, while open inputs often drift to a high state and look like a stuck-at-one defect.
In-circuit testing uses this logical method to identify structural assembly errors, verifying that every pin can transition dynamically across the full voltage range.
Rework Targeting
Pinpointing the failing node from the logic pattern allows repair technicians to inspect the specific joint for solder bridges or open circuits. This logical analysis avoids the need to visually inspect thousands of good joints under a microscope. By finding the exact failing trace, the test process reduces rework times and minimizes handling damage to the board.
