Establishing Boundary Scan Node Access Limits across Complex PCB Logic Clusters
Boundary scan access limits require balancing physical probe suppression against quantitative fault escape risks in high-density logic clusters.
Structural Fault Models
Abstraction Level
Mathematical representations of physical manufacturing defects in electronic circuits simplify the test generation process by mapping complex board-level failures to logical behaviors. These representations, known as structural fault models, assume that physical faults like solder bridges or open circuits manifest as stuck-at, open or shorted nodes. This simplification allows automated software to generate test vectors that can verify the assembly without simulating the full analog behavior.
These models focus on the correctness of the physical connections rather than the system logic. This abstraction is necessary to manage the complexity of testing millions of gates on a modern board.
Test Pattern
Test generators use these logical behaviors to calculate the exact binary inputs needed to expose a defect at an output pin. For example, a stuck-at-zero model forces a node to a high state and checks if the output remains low. This targeted test pattern ensures that any open circuit on that trace is caught.
This structured approach reduces the total number of test vectors required.
Defect Coverage
The effectiveness of a test suite is measured by the percentage of simulated faults that the patterns can detect. High coverage indicates that almost all physical assembly errors, such as bridges and cold joints, will be found during production tests. Automated tools scan the board design to identify untested nodes.
This feedback allows designers to adjust the test points.