Boundary Scan Input
A dedicated control line provides the timing reference for boundary-scan test operations in integrated circuits according to the IEEE 1149.1 standard. This synchronization is driven by the test clock tck, which manages the movement of instructions and test data through the boundary-scan architecture. This clock runs independently of the board-level system clocks to ensure that the testing can proceed under stable, controlled conditions.
The frequency of this clock is kept low to prevent noise and timing issues.
State Machine Drive
Transitions of the test access port state machine occur on the rising edge of the control pulse. The test clock tck governs the timing of these transitions, allowing the board tester to shift in data patterns and capture responses from the chip pins. Any interruption in this timing reference will stall the test sequence.
Signal Quality Requirement
Unwanted reflections on the scan lines can trigger double-clocking of the registers and ruin the test cycle. Maintaining a clean waveform for the test clock tck requires terminating the line with a resistor close to the receiver. This termination prevents overshoot and ringing from distorting the clock pulses during multi-board testing.
This signal integrity is necessary for reliable in-circuit and boundary scan testing of complex assemblies.
