Data Integrity
Software check procedures confirm the syntactic and semantic correctness of boundary scan files before board-level test development begins. This initial scan, known as bsdl verification, compares the boundary scan description language file against the physical silicon architecture of the integrated circuit. Silicon vendors supply these files to describe the internal boundary scan register structure.
Discrepancies between the file and the actual hardware register length will halt test development.
Hardware Validation
Hardware debug steps run the boundary scan sequence on a known good assembly to prove the physical pins match the file description. During this stage of bsdl verification, the test engineer connects a boundary scan controller to the test access port and reads the device identification register. The controller shifts test patterns through the registers to ensure that the boundary scan cells respond according to the language file.
Physical board traces must be free of short circuits for this check to succeed. Incorrect pin assignments in the file otherwise generate false errors that disrupt the assembly line.
Diagnostic Coverage
Diagnostic software uses the verified files to pinpoint structural board defects like open solder joints or solder bridges. Test coverage improves when bsdl verification eliminates errors in the silicon description file, allowing the test generation software to create accurate test vectors for the boundary scan chains on the board. Incorrect description files yield false failures during post-assembly board testing.
