Electromagnetic Field Suppression in Multilayer Printed Circuit Power Plane Stackups
Thin dielectric power plane pairs suppress high frequency cavity modes and radiated emissions by lowering target impedance and shifting resonant frequencies.
Anti Resonance Peak
Impedance Behavior
Impedance maximums occur within a power distribution network when the inductive and capacitive reactances of parallel components cancel each other out. An anti resonance peak describes the point where the impedance of a decoupling network reaches its highest value. This specific frequency point usually appears between the resonance frequencies of two capacitors with different values.
Engineers identify these peaks during power integrity analysis to ensure that the voltage ripple does not exceed the tolerance of the silicon device. High impedance at these frequencies limits the ability of the network to supply current.
Mitigation Strategy
Management of network peaks involves overlapping the effective frequency ranges of multiple decoupling capacitors. If an anti resonance peak aligns with the clock frequency or a major harmonic of an integrated circuit, the resulting voltage drop can cause timing errors. Adding capacitors with intermediate values or increasing the equivalent series resistance of the components can dampen the response.
This damping reduces the magnitude of the peak without requiring a complete board redesign. Probing the power planes at different locations reveals how the impedance varies across the surface.
Measurement Protocol
Vector network analyzers provide the data necessary to locate these peaks on a fabricated circuit board. A measurement showing a peak above the target impedance line indicates a failure of the decoupling scheme. Corrective actions typically involve changing the capacitor selection or the mounting inductance.