Vertical Complexity
Printed circuit boards containing more than twelve conductive layers require specialized manufacturing processes to maintain alignment and signal integrity across the entire thickness. While the definition of a high layer count varies by facility, it typically identifies panels where the cumulative thickness and the number of lamination cycles increase the risk of registration failure. These designs demand tighter control over material movement and drill accuracy.
Registration Tolerance
Accuracy in the vertical alignment of pads and holes becomes harder to sustain as more layers are added to the stackup. Shrinkage of the inner layers during multiple lamination cycles creates a cumulative offset that can result in breakout where the drill fails to hit the internal copper land. Manufacturers use advanced scaling techniques and pinless registration systems to mitigate these errors, ensuring that every conductive path remains continuous throughout the structure even as the layers accumulate.
If the offset exceeds the annular ring requirement, the entire panel is scrapped.
Aspect Ratio
Vertical interconnects in thick boards must endure mechanical stress during thermal cycling because the copper plating in the through-hole expands at a different rate than the surrounding dielectric. A high layer count often results in a high aspect ratio, which is the relationship between the board thickness and the diameter of the smallest hole. This configuration makes uniform plating difficult and increases the likelihood of barrel cracking.
Reliable plating depends on the chemistry of the bath and the agitation of the fluid.
