Circuit Verification
Electrical continuity testing identifies copper features that remain isolated from the bed of nails during fixture engagement. Unprobed nets exist when trace topology lacks designated access points or test pads required for electrical verification. Physical design software assigns these connections to interior layers or dense component clusters where mechanical access remains unavailable.
Inaccessible nodes prevent direct verification of signal integrity and isolation throughout the fabrication stage.
Design Consequence
Boards with unprobed nets rely upon secondary validation methods because physical probing proves impossible. Automated optical inspection detects opens or shorts by comparing visual geometry against master files. Flying probe systems occasionally circumvent this limitation by landing needles on component leads, yet such methods require heavy cycle time overhead.
Dense layouts with inadequate test point density increase the reliance upon statistical process control to guarantee interconnect reliability. Engineers mitigate these risks by calculating fault coverage percentage prior to final layout approval.
Standard Compliance
Manufacturing specifications often dictate the minimum percentage of net access required for successful acceptance. Compliance occurs when board files demonstrate enough test points to satisfy external diagnostic equipment. Designers must negotiate these requirements early, as retroactive changes to copper geometry typically demand complete board revision.
Inability to meet these coverage benchmarks forces manufacturers to waive continuity testing for specific internal segments. Unprobed nets represent a failure of test point planning rather than a deficiency in physical interconnect quality.
