Characterizing Intermetallic Compound Formation Rates in Micro-BGA Solder Interfaces

Micro-BGA intermetallic compound formation depends on peak reflow energy and thermal aging, where excessive layer thickness causes brittle interfacial failure.

23.09.26 13 min

Nucleation

Liquid solder interacting with a copper or nickel pad substrate triggers an immediate dissolution reaction at temperatures above the melting point. Within micro-ball grid array (micro-BGA) solder joints, where pad diameters range between 150 µm and 250 µm and solder volumes sit below 1.5 nanoliters, this interfacial reaction operates under tight volume constraints. Standard tin-silver-copper (SAC305) alloys dissolve copper rapidly during initial wetting.

Dissolution happens in milliseconds. As the molten solder matrix dissolves base copper from the substrate, local copper concentration at the liquid-solid interface swiftly surpasses the solubility limit. This localized supersaturation drives the heterogeneous nucleation of stable intermetallic compound (IMC) crystal structures along the pad surface.

The primary liquid-state reaction on bare copper yields the eta-phase binary compound Cu6Sn5. Atomic diffusion of copper atoms into the molten tin matrix proceeds under high thermal energy, creating a thin, scalloped layer across the land. In standard BGA joints with large solder mass, dissolved copper distributes into the bulk alloy volume.

Liquid tin dissolves copper fast. In micro-BGA geometry, the small bulk volume saturates with copper within seconds of reaching liquidus. This saturation limits further base metal erosion, yet it accelerates the precipitation of Cu6Sn5 crystals directly onto the interface.

Consequently, initial reflow conditions establish a continuous intermetallic layer whose base thickness depends heavily on peak thermal energy and available solder volume.

Peak reflow temperatures above 245 degrees Celsius with a time above liquidus of 65 seconds yield an initial Cu6Sn5 layer thickness of 1.2 microns on standard OSP copper pads.

Thermodynamic factors govern phase selection during liquid-state reaction. When liquid SAC solder contacts a nickel-based substrate, the reaction forms the microstructurally distinct Ni3Sn4 phase. Nickel dissolves into liquid tin at a rate significantly slower than copper, resulting in thinner initial intermetallic layers under identical reflow profiles.

However, when copper is present within the solder alloy at concentrations exceeding 0.5 weight percent, copper atoms migrate to the nickel interface, transforming the boundary phase into a ternary (Cu,Ni)6Sn5 compound. This ternary phase exhibits higher thermal stability and altered growth kinetics compared to pure binary nickel-tin phases, directly influencing the joint’s mechanical compliance.

Phase evolution continues throughout the liquid phase until cooling freezes the joint. The morphology of the newly formed Cu6Sn5 crystals transitions from small, rounded seeds into prominent scalloped structures extending into the solidifying solder bulk. High peak reflow temperatures reduce the viscosity of the liquid solder while accelerating mass transport across the interface.

This combination promotes taller scallop growth and wider inter-scallop channels. These channels serve as short-circuit diffusion paths for unreacted copper atoms, sustaining rapid growth until the temperature drops below the alloy liquidus threshold.

Whether minor micro-alloying additions like bismuth or antimony fundamentally alter the critical activation energy barrier for secondary interfacial phase transformation under sub-micron solder volumes remains debated across metallurgical literature.

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Plating

Surface finish selection governs the elemental supply available to the liquid solder joint during the brief window of reflow. PCB fabricators apply metallic coatings over copper lands to preserve solderability, but these surface layers participate directly in the interfacial chemical reaction. Organic Solderability Preservatives (OSP) evaporate or dissolve into flux upon heating, exposing bare copper directly to molten tin.

Immersion Silver (IAg) and Immersion Tin (ISn) finishes rapidly dissolve into the solder volume, leaving the underlying copper base as the primary reactive species. Electroless Nickel Immersion Gold (ENIG) and Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) introduce barrier metals that intentionally delay copper consumption, fundamentally changing the reaction kinetics.

Under ENIG coatings, the thin gold layer (typically 0.05 µm to 0.10 µm) dissolves into the molten solder within the first second of reflow. Gold dissolves without forming a planar barrier phase at the pad surface. In micro-BGA joints, the dissolved gold remains trapped within a small bulk volume.

Gold concentrations exceeding 1.5 weight percent in the bulk solder induce gold embrittlement. This condition precipitates brittle AuSn4 intermetallics within the joint bulk or directly along the interfacial IMC boundary. Below the gold layer, the electroless nickel-phosphorus deposit acts as a diffusion barrier, slowing copper migration.

The liquid tin reacts with the nickel layer to form Ni3Sn4 or (Cu,Ni)6Sn5, leaving behind an unreacted phosphorus-rich layer (P-rich layer, Ni3P) on the substrate side.

Interfacial Phase Characteristics across Board Surface Finishes
Surface Finish Primary Reflow Phase Thermal Aging Phase Barrier Consumption Rate Dominant Failure Risk
Direct Copper / OSP Cu6Sn5 (Eta) Cu3Sn (Epsilon) High (0.15 µm/s at 240°C) Kirkendall voiding
Immersion Silver Cu6Sn5 (Eta) Cu3Sn (Epsilon) High (0.14 µm/s at 240°C) Substrate copper depletion
ENIG (Ni,Cu)3Sn4 / (Cu,Ni)6Sn5 Ni3Sn4 + Ni3P Low (0.01 µm/s at 240°C) P-rich layer delamination
ENEPIG (Pd,Ni)Sn4 then (Cu,Ni)6Sn5 Complex Ni-Pd-Sn phase Extremely low (<0.005 µm/s) Brittle Pd-Sn precipitation

ENEPIG finishes introduce a palladium layer (0.02 µm to 0.10 µm) between the nickel and gold deposits. Palladium slows the wetting reaction slightly while preventing direct nickel dissolution during early liquidus. The liquid solder must dissolve both gold and palladium before interacting with the nickel substrate.

Palladium reacts with tin to form PdSn4 crystals. These crystals occasionally detach from the interface, dispersing into the solder volume. If reflow profiles run short, undissolved palladium-tin phases remain localized near the interface, creating planar stress concentrators that reduce dynamic impact strength.

Substrate finish imperfections alter interfacial kinetics across the assembly run. PCB fabricators frequently argue that minor phosphorus band segregation falls within acceptable manufacturing limits whenever visual solderability tests pass without immediate wetting failure.

Heat

Reflow profile parameters dictate the total thermal energy imparted to the solder joint, directly defining liquid-state growth kinetics. Oven settings control preheat ramp rates, thermal soak durations, peak assembly temperatures, and cooling gradients across the circuit board. Micro-BGA components exhibit small thermal mass relative to adjacent power inductors or massive connectors.

On complex assemblies, achieving complete solder wetting under heavy components without overheating micro-BGA sites presents a narrow operational window. Excess thermal energy during liquidus drives exponential acceleration of interfacial compound growth.

Time Above Liquidus (TAL) functions as the single primary operational variable governing initial intermetallic layer thickness. Liquid-state diffusion coefficients for copper in molten tin are three orders of magnitude higher than solid-state diffusion values. Thermal exposure drives growth.

Standard assembly specifications target a TAL between 45 seconds and 75 seconds for SAC305 profiles. Extending TAL to 120 seconds to accommodate thermal delta across a heavy panel doubles the initial Cu6Sn5 intermetallic thickness. Thicker layers weaken joints.

Excessively thick liquid-formed intermetallics feature rough, high-aspect-ratio scallops that protrude deep into the solder volume, creating sharp notch points where stress concentrates under mechanical shear.

Extended liquidus duration accelerates interfacial layer thickening and coarse grain formation.
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What Profile Adjustments Limit Intermetallic Growth during Reflow?

Limiting total intermetallic thickness requires tight control over peak temperature delta and forced convection cooling rates. Peak temperatures between 235 degrees Celsius and 245 degrees Celsius deliver sufficient energy for wetting without triggering excessive substrate dissolution. Cooling rates applied immediately after liquidus exit alter microstructural refinement.

Standard cooling rates of 1.5 to 2.0 degrees Celsius per second permit continued grain coarsening and scallop growth while the alloy transitions through the semi-solid mushy zone. Increasing cooling rates to 3.0 or 4.0 degrees Celsius per second through controlled multi-zone cooling fans freezes the grain structure rapidly, arresting growth and refining the final IMC grain size.

Improper thermal profile setup creates asymmetric joint microstructures across a single micro-BGA package. Edge joints near high-volume ground planes experience lower peak thermal energy and shorter effective TAL compared to center joints positioned under a thin die. Center joints exhibit thicker intermetallic layers and larger grain structures, making them susceptible to early fatigue crack propagation during operating thermal cycles.

Exceeding thermal profile limits during reflow turns ductile solder-pad interfaces into rigid failure planes that shear under board flexure during downstream handling.

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Shear

Mechanical integrity at the package interface degrades over time as solid-state diffusion continues during operational thermal exposure. Solder joints operating inside high-temperature environments (85°C to 125°C) undergo continuous atomic migration. Copper atoms from the substrate diffuse through the existing Cu6Sn5 intermetallic layer to react with tin, giving rise to a secondary phase: epsilon-phase Cu3Sn.

The Cu3Sn layer forms directly between the base copper substrate and the overlying Cu6Sn5 layer. This dual-layer structure introduces structural instability due to lattice parameter mismatches between adjacent phase boundaries.

Solid-state diffusion rates follow an Arrhenius relationship where phase layer growth thickness scales predictably with time and absolute temperature:

x(t) = ( x0^2 + 2 D0 exp( -Q / ( R T ) ) t )^0.5

In this relationship, x(t) represents total intermetallic thickness at time t, x0 is the initial post-reflow layer thickness, D0 is the pre-exponential diffusion factor, Q represents activation energy (typically 80 to 105 kJ/mol for copper-tin phases), R is the universal gas constant, and T is absolute temperature in Kelvin. At operating temperatures below 80 degrees Celsius, Cu3Sn formation remains slow. Above 100 degrees Celsius, Cu3Sn layer growth accelerates rapidly, consuming base copper and generating atomic vacancy concentration gradients.

Kirkendall void formation accompanies thick Cu3Sn growth. Copper diffuses outward through the Cu3Sn layer toward the tin matrix substantially faster than tin diffuses inward toward the copper substrate. This unbalanced, directional atom flux leaves behind a high concentration of vacant lattice sites at the Cu to Cu3Sn interface.

Over hundreds of operating hours, these vacancy points coalesce into microscopic voids. Voids reduce effective bond area. Under high-strain-rate mechanical loading, such as board drop tests or thermal shock excursions, these Kirkendall void networks act as continuous crack propagation paths, causing sudden low-energy brittle fractures.

Consider a micro-BGA joint constructed with SAC305 solder on an OSP copper substrate. Initial reflow produces a baseline Cu6Sn5 thickness of 1.0 micron with negligible Cu3Sn presence. Operating the device at an elevated temperature of 125 degrees Celsius (398.15 K) for 1,000 hours drives solid-state growth.

Assuming a combined effective diffusion coefficient of 1.2 x 10^-13 cm^2/s at this temperature, the growth calculation yields a secondary Cu3Sn layer thickness of approximately 0.9 microns and expands the total interfacial intermetallic layer (Cu6Sn5 + Cu3Sn) to roughly 2.3 microns. At this threshold, Kirkendall void density along the copper boundary reaches critical levels, decreasing high-speed ball shear strength by up to 45 percent compared to unaged baseline samples.

  • Brittle Interfacial Cleavage occurs when dynamic stress fractures the joint along the planar Cu3Sn phase boundary under high strain rates.
  • Kirkendall Micro-Void Coalescence degrades static load capacity as vacancy clusters merge along the primary copper pad interface during high-temperature storage.
  • Gold Embrittlement Spalling manifests when dense concentrations of AuSn4 needles migrate to the solder-IMC interface, creating localized detachment planes.
  • Phosphide Layer Delamination arises on ENIG finishes when nickel consumption leaves a brittle Ni3P hyper-passive band prone to shock failure.
According to IPC-TM-650 Method 2.4.43, micro-BGA ball shear testing requires high-speed impact rates above 1.0 meter per second to successfully differentiate ductile bulk solder deformation from brittle interfacial failure.

Solder joints with intermetallic layer thicknesses exceeding a third of the overall standoff height consistently fail along the substrate boundary rather than within the bulk alloy.

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Metrology

Quantifying micron-scale phase layers requires destructive analytical methods structured to isolate the substrate interface without inducing artifact deformation. Standard cross-sectional preparation involves potting sample coupons in cold-curing epoxy resins. Micro-BGA joints present small physical dimensions, making target alignment difficult during mechanical grinding.

Automated polishing equipment utilizes silicon carbide papers followed by diamond suspensions down to 0.25 microns. Etching isolates interfacial boundaries. Final polishing with colloidal silica (0.05 micron) at low platen speeds removes smeared solder alloy from the interface, preserving clear phase boundaries for optical and electron microscopy.

  1. Route test coupons from the panel using low-stress diamond sawing to avoid mechanical micro-cracking at the joint boundary.
  2. Mount coupons vertically in epoxy resin using precision alignment clips to ensure grinding runs perpendicular to the PCB pad plane.
  3. Grind samples down to the center row of micro-BGA spheres using 800 and 1200 grit silicon carbide paper under light constant force.
  4. Polish sequentially using 3-micron and 1-micron diamond suspensions on napless cloths to maintain flat edge retention across soft solder and hard pad materials.
  5. Apply a final 0.05-micron colloidal silica polish for 90 seconds to eliminate micro-smearing without rounding the interfacial boundary.
  6. Etch the polished surface briefly with a ammonium hydroxide and hydrogen peroxide solution to contrast intermetallic phase layers against the bulk solder matrix.

Scanning Electron Microscopy (SEM) operating in Backscattered Electron (BSE) mode provides the primary visual resolution necessary to measure sub-micron intermetallic structures. BSE imaging highlights compositional atomic number contrast, making the lighter Cu3Sn layer distinctly darker than adjacent Cu6Sn5 and base copper regions. Energy-Dispersive X-ray Spectroscopy (EDX) point analyses confirm stoichiometric elemental ratios, identifying specific binary and ternary phases.

Visual checks reveal nothing here. Non-destructive X-ray inspection systems lack the spatial resolution required to detect micron-scale intermetallic growth or Kirkendall void clusters, highlighting the necessity of coupon-based destructive testing during process qualification.

Analytical Method Capabilities for Micro-BGA Interfacial Analysis
Analytical Technique Spatial Resolution Target Phase Identification Destructive Status Primary Measurement Role
Optical Microscopy 0.5 µm Coarse phase layers only Destructive Routine cross-section screening
SEM (BSE Mode) 5 nm Cu6Sn5 vs Cu3Sn vs Ni3Sn4 boundary Destructive Precise phase thickness measurement
EDX Spectroscopy 1.0 µm spot size Stoichiometric atomic ratio quantification Destructive Chemical compound verification
X-ray Microscopy (3D XRM) 0.5 µm voxel size Macro-voids and solder bridging Non-destructive Assembly-level structural inspection
Acoustic Microscopy (C-SAM) 10 µm planar Interfacial delamination and cracks Non-destructive Post-environmental stress screening
IPC-A-610 Class 3 acceptance mandates complete wetting across the land interface without continuous interfacial micro-cracking or structural pad detachment.

Specifying IPC-TM-650 Method 2.1.1.2 within the assembly contract forces the fabricator to archive polished microsection coupons for every production lot before release.

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Stipulation

Technical purchase contracts must anchor interfacial qualification targets directly to verifiable profile metrics and destructive batch testing. Relying solely on electrical continuity tests or visual automated optical inspection (AOI) leaves assembly buyers exposed to latent field failure risks driven by bad interfacial kinetics. Procurement specifications should define maximum allowable post-reflow IMC thickness thresholds alongside mandatory thermal profile logging for every SMT line run.

Contract lines enforce process control.

Quality agreements must account for thermal reflow history limits, including secondary reflow passes and component rework cycles. Double-sided board assembly subjects bottom-side micro-BGA components to a second complete reflow excursion. This secondary pass increases initial Cu6Sn5 layer thickness by 40 to 60 percent while initiating early Cu3Sn formation.

BGA rework protocols that utilize localized hot-gas rehead systems often apply uncontrolled, long-duration thermal cycles to adjacent components. Standard contracts must cap total allowable reflow passes at three and mandate thermal shielding across adjacent micro-BGA sites during localized rework operations.

Line qualification dossiers require documentation confirming component and board pad surface finish traceabilities. Lot-to-lot variations in ENIG plating chemistry or OSP coating thickness alter interfacial reaction rates unpredictably. Establishing clear baseline parameters protects both assembly buyers and EMS providers from ambiguous failure liabilities.

SMT process audits must verify that peak reflow profiles match original thermal models validated during pre-production qualification runs.

Establishing clear quantitative limits on intermetallic compound growth within manufacturing specifications guarantees structural interconnect integrity throughout the operational lifecycle of high-reliability micro-BGA assemblies.

Nomenclature

Surface Finish

Protective Coating ~ Metallic or organic layer applied to the exposed copper pads of a printed circuit board prevents oxidation and ensures reliable component attachment.

Cu3Sn

Compound Structure ~ An intermetallic compound of copper and tin forms at the interface between copper pads and tin-bearing solder during the reflow process.

ENIG

Surface Finish ~ Electroless nickel immersion gold provides a flat metallic base for solder joints and wire bonds on printed circuit boards.

Activation Energy

Kinetic Constant ~ Thermodynamic parameter defining the minimum energy gap that particles must cross to initiate a chemical or physical transformation within a component package.

ENEPIG

Plating Chemistry ~ Electrolytic nickel electroless palladium gold, commonly known as enepig, is a multilayer metallic surface finish deposited onto printed circuit board copper pads during fabrication to protect underlying metal from oxidation.

Intermetallic Layer

Bond Morphology ~ An atomic scale reaction zone occurs at the interface of a solder alloy and a copper base metal during the thermal cycles of the reflow process.

Intermetallic Compound

Chemical Structure ~ Formation of distinct crystalline phases at the boundary between a metal pad and molten solder establishes the essential atomic connection in a solder joint.

Scanning Electron Microscopy

Beam Interaction ~ Focused electron imaging provides high magnification topographic analysis for printed circuit board cross sections during failure verification.

Thermal Profile

Temperature Graph ~ Time-versus-temperature process graphing maps the thermal trajectory an electronic assembly experiences while passing through a conveyorized reflow oven.

Secondary Reflow

Thermal Sequencing ~ A thermal cycle involves a second pass through the convection furnace to finalize the bonding of components on the bottom side of a circuit board.

Cross-Sectional Analysis

Metallurgical Audit ~ Slicing a populated printed circuit board along a defined plane exposes internal solder joints for micrographic inspection during contract manufacturing verification.

Kirkendall Voiding

Interfacial Migration ~ Intermetallic layer growth beneath a solder joint generates vacancies through asymmetric atomic diffusion rates across the boundary.

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